PCI CD and PCI CDa PCI CD and PCI CDa Revision: I December 2004 Document Number: 008-00965-06 Template: edt.
PCI CD and PCI CDa Control Information Control Item Details Document Owner Mark Mason/Dan Boer Information Label EDT Public Supersedes None File Location frm:/pcicd/pcicd.doc Document Number 008-00965-06 Revision History Revision Date Revision Description Originator Draft 20-Aug-03 Convert from FrameMaker to Word S Vasil A 11-Jan-04 Added Input/Output section; general cleanup S Vasil B 18-Mar-04 Updated “Upgrading the Firmware” section. Added CDa pinout.
PCI CD and PCI CDa The information in this document is subject to change without notice and does not represent a commitment on the part of Engineering Design Team, Inc. The software described in this document is furnished under a license agreement or nondisclosure agreement. The software may be used or copied only in accordance with the terms of the agreement. Engineering Design Team, Inc.
PCI CD and PCI CDa Contents Overview ................................................................................................................................5 Features ..............................................................................................................................5 Installation .............................................................................................................................6 Verifying the Installation.........................................
PCI CD and PCI CDa Overview The PCI Bus Configurable DMA (PCI CD) board is a single-slot, 16-bit parallel input/output interface for PCI bus-based computer systems. It is designed for continuous input or output between a user device and PCI bus host memory. This interface is typically used to move data between a PCI bus host computer and devices such as scanners, plotters, imaging devices, or research prototypes. The PCI CD uses a simple synchronous protocol for transferring data.
PCI CD and PCI CDa Installation If you are using a Dell computer, you should be aware that for some models, Dell recommends high data rate cards (such as video and frame grabbers) be placed in one of the first two slots (closest to the AGP connector). The other two PCI bus slots are only recommended for lower speed devices such as audio devices or modems. Caution: Be sure to use appropriate static protection to prevent damaging your PCI CD/CDa.
PCI CD and PCI CDa Verifying the Installation To verify that installation was successful and that the PCI CD/CDa is operating correctly: 1. Run Pcicd Utilities (Windows NT) or cd to /opt/EDTpcd (UNIX). 2. At the command prompt, enter: xtest 4096 Outcome: The PCI CD/CDa returns test status information. You will be prompted to press Return at certain steps.
PCI CD and PCI CDa To reselect the default Xilinx bitfile at a later time, rerun pcdrequest, or edit the pcdload script file by hand. Note: xtest downloads its own test bitfile automatically; after running xtest, run pcdload to reload the default bitfile. The PCI CD/CDa boards are synchronous interfaces—they send a clock signal with all data and control signals. The PCI CD stores inputs only at the rising edge of the receive timing (RXT) signal that comes from the user device.
PCI CD and PCI CDa PCI CD You must choose the source for the TXT signal when the driver is loaded. We recommend using the RXT input for TXT timing. Even if the PCI CD internal oscillator is used to time the user device, the user device can use the PCI CD signal SENDT (send timing) to drive device outputs. It can then be sent back as the RXT signal. For most installations, choose either external clock with TXT looped from RXT, or internal clock from the PCI CD.
PCI CD and PCI CDa pkgrm EDTpcd For further details, consult your operating system documentation, or call Engineering Design Team. Linux Systems To remove the PCI CD/CDa driver on Linux systems: 1. 2. 3. 4. Enter: cd /opt/EDTpcd Enter: make unload Enter: cd / Enter: rm –rf /opt/EDTpcd Windows NT Systems To remove the PCI CD/CDa toolkit on Windows NT systems, use the Windows NT Add/Remove utility. For further details, consult your Windows NT documentation.
PCI CD and PCI CDa pciload help Document Number: 008-00965-06 Template: edt.
PCI CD and PCI CDa Input and Output The PCI CD/CDa device driver can perform two kinds of DMA transfers: continuous and noncontinuous. To perform continuous transfers, use ring buffers. The ring buffers are a set of buffers that applications can access continuously, reading and writing as required. When the last buffer in the set has been accessed, the application then cycles back to the first buffer.
PCI CD and PCI CDa EdtDev *edt_p = edt_open_channel("pcd", 1, 2) ; char buf[1024] ; int numbytes, outfd = open("outfile", 1) ; /* * Because read()s are noncontinuous, unless is there hardware * handshaking there will be gaps in the data between each read().
PCI CD and PCI CDa FIFO Flushing First-in, first-out (FIFO) memory buffers are used to smooth data transmission between different types of data sinks internal to PCI DV boards. For instance, the FIFO stores information processed by the user interface Xilinx until the PCI Xilinx retrieves it across the PCI bus. The PCI bus normally sends information in bursts, so the FIFO allows this same information to be sent smoothly.
PCI CD and PCI CDa 2. When exiting the program, one of the following two conditions must be met before the EDT driver is used again: • All threads spawned by a main program must be joined with the main program after they exit and before the main program exits; or • If the main program does not wait for the child threads to exit, then any program that is run following the main program must wait for all the child threads to exit.
PCI CD and PCI CDa Routine Description edt_last_buffer_timed Like edt_last_buffer but also returns the time at which the dma was complete on this buffer. edt_configure_ring_buffers Configures the ring buffers. edt_buffer_addresses Returns an array of addresses referencing the ring buffers. edt_disable_ring_buffers Stops DMA transfer, disables ring buffers and releases resources. edt_ring_buffer_overrun Detects ring buffer overrun which may have corrupted data.
PCI CD and PCI CDa Routine edt_set_firstflush Description Tells whether and when to flush FIFOs before DMA. edt_flush_fifo Flushes the EDT Product FIFOs. edt_get_goodbits Returns the number of bits from the remote device. Control edt_set_event_func Defines a function to call when an event occurs. edt_remove_event_func Removes a previously set event function. edt_reg_read Reads the contents of the specified EDT Product register. edt_reg_write Writes a value to the specified EDT Product register.
PCI CD and PCI CDa Arguments devname unit a string with the name of the EDT Product board. For example, “edt”. specifies the device unit number Return A handle of type (EdtDev *), or NULL if error. (The structure(EdtDev *) is defined in libedt.h.) If an error occurs, check the errno global variable for the error number. The device name for the EDT Product is “edt”.
PCI CD and PCI CDa edt_parse_unit Description Parses an EDT device name string. Fills in the name of the device, with the default_device if specified, or a default determined by the package, and returns a unit number. Designed to facilitate a flexible device/unit command line argument scheme for application programs. Most EDT example/utility programs use this susubroutine to allow users to specify either a unit number alone or a device/unit number concatenation.
PCI CD and PCI CDa Return The return value from read, normally the number of bytes read; –1 is returned in case of error. Call edt_perror() to get the system error message. Note If using timeouts, call edt_timeouts after edt_read returns to see if the number of timeouts has incremented. If it has incremented, call edt_get_timeout_count to get the number of bytes transferred into the buffer.
PCI CD and PCI CDa Arguments edt_p bufnum device handle returned from edt_open or edt_open_channel Number of buffers to release to the driver for transfer. An argument of 0 puts the driver in free running mode, and transfers run continuously until edt_stop_buffers() is called. Return 0 on success; –1 on error. If an error occurs, call edt_perror() to get the system error message. edt_stop_buffers Description Stops DMA transfer after the current buffer has completed.
PCI CD and PCI CDa edt_done_count Description Returns the cumulative count of completed buffer transfers in ring buffer mode. Syntax #include "edtinc.h" int edt_done_count(EdtDev *edt_p); Arguments edt_p device handle returned from edt_open or edt_open_channel. Return The number of completed buffer transfers. Completed buffers are numbered consecutively starting with 0 when edt_configure_ring_buffers() is invoked.
PCI CD and PCI CDa Syntax #include "edtinc.h" void *edt_wait_buffers(EdtDev *edt_p, int count); Arguments edt_p device handle returned from edt_open or edt_open_channel count How many buffers to block for. Completed buffers are numbered relatively; start each call with 1. Return Address of last completed buffer on success; NULL on error. If an error occurs, call edt_perror() to get the system error message.
PCI CD and PCI CDa Arguments edt_p device handle returned from edt_open or edt_open_channel count buffer number for which to block. Completed buffers are numbered cumulatively starting with 0 when the EDT Product is opened. timep pointer to an array of two unsigned integers. The first integer is seconds, the next integer is microseconds representing the system time at which the buffer completed. Return Address of last completed buffer on success; NULL on error.
PCI CD and PCI CDa edt_set_buffer(edt_p, 0); Return 0 on success, -1 on failure. See Also edt_stop_buffers(), edt_done_count(), edt_get_todo() edt_set_buffer_size Description Used to change the size or direction of one of the ring buffers. Almost never used. Mixing directions requires detailed knowledge of the interface since pending preloaded DMA transfers need to be coordinated with the interface fifo direction.
PCI CD and PCI CDa Arguments edt_p device struct returned from edt_open nSkipped pointer to an integer which will be filled in with number of buffers skipped, if any. Syntax unsigned char *edt_last_buffer(EdtDev *edt_p, int *nSkipped) Example int skipped_bufs; u_char *buf; buf=edt_last_buffer(edt_p, &skipped_bufs); Return Address of the image.
PCI CD and PCI CDa edt_configure_ring_buffers Description Configures the EDT device ring buffers. Any previous configuration is replaced, and previously allocated buffers are released. Buffers can be allocated and maintained within the EDT device library or within the user application itself. Syntax #include "edtinc.
PCI CD and PCI CDa edt_disable_ring_buffers Description Disables the EDT device ring buffers. Pending DMA is cancelled and all buffers are released. Syntax #include "edtinc.h" int edt_disable_ring_buffers(EdtDev *edt_p); Arguments edt_p device handle returned from edt_open or edt_open_channel Return 0 on success; –1 on error. If an error occurs, call edt_perror() to get the system error message.
PCI CD and PCI CDa edt_configure_block_buffers Description Similar to edt_configure_ring_buffers, except that it allocates the ring buffers as a single large block, setting the ring buffer addresses from within that block. This allows reading or writing buffers from/to a file in single chunks larger than the buffer size, which is sometimes considerable more efficient. Buffer sizes are rounded up by PAGE_SIZE so that DMA occurs on a page boundary.
PCI CD and PCI CDa Return void See Also edt_startdma_reg(), edt_reg_write(), edt_reg_read() edt_enddma_action Description Specifies when to perform the action at the end of a dma transfer as specified by edt_enddma_reg(). A common use of this is to write to a register which signals an external device that dma is complete, or to change the state of a signal which will be changed at the start of dma, so the external device can look for an edge. The default is no end of dma action.
PCI CD and PCI CDa edt_startdma_reg(edt_p, PDV_CMD, PDV_ENABLE_GRAB); Return void See Also edt_startdma_action() edt_abort_dma Description Stops any transfers currently in progress, resets the ring buffer pointers to restart on the current buffer. Syntax #include "edtinc.h" int edt_abort_dma(EdtDev *edt_p); Arguments edt_p device handle returned from edt_open or edt_open_channel. Return 0 on success; –1 on error. If an error occurs, call edt_perror() to get the system error message.
PCI CD and PCI CDa Arguments edt_p device handle returned from edt_open or edt_open_channel Return The number of bytes transferred, as described above. edt_timeouts Description Returns the number of read and write timeouts that have occurred since the last call of edt_open. Syntax #include "edtinc.
PCI CD and PCI CDa EDT_TIMEOUT_NULL no extra action taken EDT_TIMEOUT_BIT_STROBE flush any valid bits left in input circuits of SSDIO. Return No return value. edt_get_timeout_goodbits Description Returns the number of good bits in the last long word of a read buffer after the last timeout. This routine is called after a timeout, if the timeout action is set to EDT_TIMEOUT_BIT_STROBE. (See edt_set_timeout_action on page 32.) Syntax #include "edtinc.
PCI CD and PCI CDa edt_get_rtimeout Description Gets the current read timeout value: the number of milliseconds to wait for DMA reads to complete before returning. Syntax #include "edtinc.h" int edt_get_rtimeout(EdtDev *edt_p); Arguments edt_p device handle returned from edt_open or edt_open_channel Return The number of milliseconds in the current read timeout period.
PCI CD and PCI CDa edt_set_wtimeout Description Sets the number of milliseconds for data write calls, such as edt_write(), to wait for DMA to complete before returning. A value of 0 causes the I/O operation to wait forever—that is, to block on a write. Edt_set_wtimeout affects edt_wait_for_buffers (see page XX) and edt_write (see page XX). Syntax #include "edtinc.
PCI CD and PCI CDa Syntax int edt_get_reftime(EdtDev *edt_p, u_int *timep) Arguments edt_p device struct returned from edt_open timep pointer to an unsigned integer array bufnum buffer index, or number of buffers completed Example int timestamp[2]; edt_get_regtime(edt_p, timestamp); Return 0 on success, -1 on failure. Fills in timestamp pointed to by timep.
PCI CD and PCI CDa edt_get_burst_enable Description Returns the value of the burst enable flag, determining whether the DMA master transfers as many words as possible at once, or transfers them one at a time as soon as the data is acquired. Burst transfers are enabled by default to optimize use of the bus. For more information, see edt_set_burst_enable on page 37. Syntax #include "edtinc.
PCI CD and PCI CDa Example int application_should_already_know_this; application_should_already_know_this=edt_get_firstflush(edt_p); Return Yes See Also edt_set_firstflush edt_set_firstflush Description Tells whether and when to flush the FIFOs before DMA transfer. By default, the FIFOs are not flushed. However, certain applications may require flushing before a given DMA transfer, or before each transfer. Syntax #include "edtinc.
PCI CD and PCI CDa edt_get_goodbits Description Returns the current number of good bits in the last long word of a read buffer (0 through 31). Syntax #include "edtinc.h" int edt_get_goodbits(EdtDev *edt_p); Arguments edt_p device handle returned from edt_open or edt_open_channel Return Number 0–31 represents the number of good bits in the 32-bit word of the current read buffer. edt_set_event_func Description Defines a function to call when an event occurs.
PCI CD and PCI CDa EDT_EVENT_PCD_STAT2 Interrupt occurred on Status 2 line PCI CD EDT_EVENT_PCD_STAT3 Interrupt occurred on Status 3 line PCI CD EDT_EVENT_PCD_STAT4 Interrupt occurred on Status 4 line PCI CD EDT_EVENT_ENDDMA DMA has completed ALL func The function you’ve defined to call when the event occurs. data Pointer to data block (if any) to send to the function as an argument; usually edt_p. continue Flag to enable or disable continued event notification.
PCI CD and PCI CDa descriptions in the section entitled “Hardware.” Return The value of the register. edt_reg_write Note Use this routine with care; it writes directly to the hardware. An incorrect value can crash your system, possibly causing loss of data. Description Write the specified value to the specified register. Use this routine instead of using ioctls. Syntax #include "edtinc.
PCI CD and PCI CDa edt_reg_or Note Use this routine with care; it writes directly to the hardware. An incorrect value can crash your system, possibly causing loss of data. Description Performs a bitwise logical OR of the value of the specified register and the value provided in the argument; the result becomes the new value of the register. Use this routine instead of using ioctls. Syntax #include "edtinc.
PCI CD and PCI CDa Syntax int edt_set_foicount(EdtDev *edt_p, int unit) Arguments edt_p device struct returned from edt_open unit unit number of RCI unit Example int nextunit; nextunit=3; edt_set_foiunit(edt_p, nextunit); Return 0 on success, -1 on failure See Also pdv_serial_write(), edt_reg_write(), edt_reg_read(), pdv_serial_read() edt_intfc_write Description A convenience routine, partly for backward compatability, to access the XILINX interface registers.
PCI CD and PCI CDa edt_intfc_read Description A convenience routine, partly for backward compatability, to access the XILINX interface registers. The register descriptors used be edt_reg_write() can also be used, since edt_intfc_read masks off the offset.
PCI CD and PCI CDa edt_intfc_read_short Description A convenience routine, partly for backward compatability, to access the XILINX interface registers. The register descriptors used be edt_reg_write() can also be used, since edt_intfc_read_short masks off the offset.
PCI CD and PCI CDa edt_intfc_read_32 Description A convenience routine, partly for backward compatability, to access the XILINX interface registers. The register descriptors used be edt_reg_write() can also be used, since edt_intfc_read_32 masks off the offset.
PCI CD and PCI CDa Arguments nbytes number of bytes of memory to allocate. Example unsigned char *buf = edt_alloc(1024); Returns The address of the allocated memory, or NULL on error. If NULL, use edt_perror on page 47 to print the error. edt_free Description Convenience routine to free the memory allocated with pdv_alloc (above). Syntax #include "edtinc.h" int edt_free(unsigned char *buf) Arguments buf Address of memory buffer to free.
PCI CD and PCI CDa Syntax #include "edtinc.h" int edt_errno(void) Arguments None. Return 32-bit integer representing the operating system-dependent error number generated by an error. Example if ((edt_p = edt_open("p11w",0))==NULL { int error_num; edt_perror("edt_open"); error_num = edt_errno(edt_p); } edt_access Description Determines file access, independent of operating system. This a convenience routine that maps to acccess() on Unix/Linus systems and _access() on Windows systems.
PCI CD and PCI CDa int edt_get_bitpath(EdtDev *edt_p, char *bitpath, int size); Arguments edt_p device handle returned from edt_open or edt_open_channel bitpath address of a character buffer of at least 128 bytes size number of bytes in the above character buffer Return 0 on success, -1 on failure EDT Message Handler Library The edt error library provides generalized error and message handling for the edt and pdv libraries.
PCI CD and PCI CDa EDT_MSG_INFO_1 (defined as EDTAPP_MSG_INFO_1 | EDTLIB_MSG_INFO_2 | PDVLIB_MSG_INFO_2) EDT_MSG_INFO_2 (defined as EDTAPP_MSG_INFO_2 | EDTLIB_MSG_INFO_2 | PDVLIB_MSG_INFO_2) Message levels are defined by flag bits, and each bit can be set or cleared individually. So for example if you want a message handler to be called for fatal and warning application messages only, you would specify EDTAPP_MSG_FATAL | EDTAPP_MSG_WARNING.
PCI CD and PCI CDa edt_msg Description Submits a message to the default message handler, which will conditionally (based on the flag bits) send the message as an argument to the default message handler function. Uses the default message handle, and is equivalent to calling edt_msg_output(edt_msg_default_handle(), ...). To submit a message for handling from other than the default message handle, use edt_msg_output. Syntax int edt_msg(int level, char *format, ...
PCI CD and PCI CDa edt_msg_set_level(msg_p, EDT_MSG_FATAL | EDT_MSG_WARNING); if (edt_access(fname, 0) != 0) edt_msg_output(msg_p, EDTAPP_MSG_WARNING, "file '%s' not found", fname); edt_msg_close Description Closes and frees up memory associated with a message handle. Use only on message handles that have been explicitly initialized by edt_msg_init. Do not try to close the default message handle.
PCI CD and PCI CDa Arguments the message handle msg_p Example See edt_msg Return Void See Also edt_msg, edt_msg_set_level edt_msg_set_msg_file Description Sets the output file pointer for the message handler. Expects a file handle for a file that is already open.
PCI CD and PCI CDa edt_sysperror(EDT_FATAL, "file.txt"); Return 0 on success, -1 on failure See Also edt_perror Document Number: 008-00965-06 Template: edt.
PCI CD and PCI CDa PCI CD Output Clock Generation The output clock is generated from a phase-locked loop (PLL) oscillator, a reference crystal, and programmable dividers. Because each of these components has physical limits to its operation, it may not be possible to get exactly the frequency desired. To get the expected results, you need to understand how the clock generator operates. Figure 1 diagrams how the final value is generated.
PCI CD and PCI CDa For example, to achieve 15 MHz using a PCI CD-20 (fxtal = 10 MHz), the following numbers work (although they are not unique): N=60, V=1, M=10, R=2, H=1, L=1, X=1 To achieve 125 Hz in a PCI CD-20 (fxtal = 10 MHz), the following numbers work (although they are not unique): N=50, V=1, M=10, R=8, H=5, L=50, X=100 The output clock has a wide range of values, but the frequency limitations at different stages limits the ultimate ability to exactly hit any specific frequency.
PCI CD and PCI CDa Arguments edt_p device handle returned from edt_open target desired output frequency in Hz xtal base frequency of the PCI CD board: PCI CD use XTAL20 PCI CD use XTAL60 Verbose a value of 1 prints a description to stdout, useful for debugging ; a value of 0 turns off verbose output Return The actual frequency, in Hertz, computed for the edt_pll structure.
PCI CD and PCI CDa void edt_set_out_clock(EdtDev *edt_p, edt_pll *pll); Arguments edt_p device handle returned from edt_open. pll the structure containing the values necessary to set the phase-locked loop circuit, as described in Figure 1. Return None. Document Number: 008-00965-06 Template: edt.
PCI CD and PCI CDa PCI CDa Output Clock Generation The PCI CDa has one programmable clock with a range of 168 Hz to 100 MHz. Most frequencies between these extremes can be achieved with little error. (Some FPGA bitfiles may allow an extended range of up to 200 MHz.) The programmable clock has an ICS307-02 clock generator (from Integrated Circuit Systems, www.icst.com) followed by a 14-bit programmable divider. The reference clock to the ICS307-02 is 10.3861 MHz. Note: Seee set_ss_vco.c as an example.
PCI CD and PCI CDa edt_set_out_clk_ics307 Description Sets the frequency output on the PCI CDa board, using parameters computed by edt_find_vco_frequency_ics307. The clock_channel command selects the clock channel to which this should be applied. The CDa has only one clock channel; therefore, the channel ID should always be set to 0. Syntax #include “edtinc.h” #include “edt_ss_vco.
PCI CD and PCI CDa Hardware Interface Protocol This section describes how to connect your device to an PCI CD/CDa interface, including the electrical characteristics of the signal, the signal descriptions, the timing specifications, and the connector pinout. Electrical Interface The PCI CD/CDa uses differential data transmission to transmit data at very high rates over long distances through noisy environments. Differential transmission nullifies the effects of ground shifts and noise.
PCI CD and PCI CDa Pseudo-ECL The PCI CD-40 DMA interface protocol uses AT&T pseudo-emitter-coupled logic (PECL) signal levels. Pseudo-ECL levels are ECL levels that are shifted by 5 volts to run on a single +5 volts power supply. These devices are excellent for minimizing electromagnetic interference where data must be transmitted at very high speeds.
PCI CD and PCI CDa Signals The hardware flow control protocol assumes that FIFO or memory buffers on both ends implement almost-full and almost-empty thresholds. Therefore, when a “not ready to accept data” signal is sent to the transmitting device, the receiver can still accommodate enough data to allow for cable delay and synchronization. Signal PCI CD I/O Description DAT(15:0) I/O Sixteen bi-directional data lines for DMA data. STAT(3:0) I Four general-purpose control inputs.
PCI CD and PCI CDa Signal PCI CD I/O Description data after DNR is presented to the input pins. Table 4. Signals Timing The clock and data output timing is specified at the pins of the PCI CD/CDa connector. PCI CD-20 PCI CD-40 PCI CD-60 Clock frequency 0-10 MHz 0-20 MHz 0-30 MHz Clock duty cycle 50% ± 10 ns 50% ± 5 ns 50% ± 5 ns Input minimum setup time 20 ns 5 ns 5 ns Input minimum hold time 25 ns 6 ns 6 ns 10 ns 10 ns Output maximum propagation delay 20 ns Table 5.
PCI CD and PCI CDa Connector Pinout The PCI CD/CDa board uses a high-density 80-pin I/O connector, AMP part number 787190-8. The cable uses a straight-shielded backshell (AMP P/N 749196-2) or right angle backshell (AMP P/N 749621-8). The following pinout describes the connection from the PCI CD/CDa board to the cable. Note: Do not connect your own circuits to the unused pins, as they may be internally connected to the PCI CD/CDa.
PCI CD and PCI CDa AMP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Document Number: 008-00965-06 Template: edt.
PCI CD and PCI CDa AMP Signal AMP Signal 1 2* 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Ground Ground DAT4+ DAT4– DAT5+ DAT5– DAT6+ DAT6– DAT7+ DAT7– DAT12+ DAT12– DAT13+ DAT13– DAT14+ DAT14– DAT15+ DAT15– SPARE 0+ +5V SPARE 1+ SPARE 2+ Ground STAT0+ STAT0– STAT1+ STAT1– STAT2+ STAT2– STAT3+ STAT3– FUNCT0+ FUNCT0– FUNCT1+ FUNCT1– FUNCT2+ FUNCT2– FUNCT3+ FUNCT3– Ground 41 42* 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
PCI CD and PCI CDa P3 Channel–Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CH1–25 CH1–25 CH2–3 CH2–4 CH2–5 CH2–6 CH2–7 CH2–8 CH2–9 CH2–10 CH4–3 CH4–4 CH4–5 CH4–6 CH4–7 CH4–8 CH4–9 CH4–10 CH3–25 CH2–1 CH2–2 CH4–1 CH4–2 CH3–25 Document Number: 008-00965-06 Template: edt.
PCI CD and PCI CDa P3 Channel–Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CH1–25 CH1–25 CH2–3 CH2–4 CH2–5 CH2–6 CH2–7 CH2–8 CH2–9 CH2–10 CH4–3 CH4–4 CH4–5 CH4–6 CH4–7 CH4–8 CH4–9 CH4–10 P3 Channel–Pin Signal Ground 41 CH2–25 Ground 42 CH2–25 CH2D0+ 43 CH1–3 CH2D0– 44 CH1–4 CH2D1+ 45 CH1–5 CH2D1– 46 CH1–6 CH2D2+ 47 CH1–7 CH2D2– 48 CH1–8 CH2D3+ 49 CH1–9 CH2D3– 50 CH1–10 CH4D0+ 51 CH3–3 CH4D0– 52 CH3–4 CH4D1+ 53 CH3–5 CH4D1– 54 CH3–6
PCI CD and PCI CDa Document Number: 008-00965-06 Template: edt.
PCI CD and PCI CDa Registers The PCI CD/CDa has two memory spaces: the memory-mapped registers and the configuration space. Expansion ROM and I/O space are not implemented. Applications can access the PCI CD/CDa registers through the DMA library routines edt_reg_read or edt_reg_write using the name specified under “Access,” or if necessary by means of ioctl calls with PCI CD/CDa-specific parameters, as defined in the file pcd.h.
PCI CD and PCI CDa Bit Name Value Bit Name Value 0–4 reserved 0 10 DEVSEL Timing 0 5 66 MHz Capable 1 11 Signaled Target Abort implemented 6 UDF Supported 0 12 Received Target Abort implemented 7 Fast Back-to-back Capable 0 13 Received Master Abort implemented 8 Data Parity Error Detected implemented 14 Signaled System Error implemented 9 DEVSEL Timing 1 15 Detected Parity Error implemented Table 12.
PCI CD and PCI CDa Address Bits 31 16 15 0 0xCC remote Xilinx data 0xC8 PCI interrupt status 0xC4 PCI interrupt and remote Xilinx configuration 0x84 not used flash ROM data 0x80 flash ROM address 0x20 not used 0x1C scatter-gather DMA next count and control 0x18 scatter-gather DMA current count and control 0x14 scatter-gather DMA next address 0x10 scatter-gather DMA current address 0x0C main DMA next count and control 0x08 main DMA current count and control 0x04 main DMA next a
PCI CD and PCI CDa The scatter-gather DMA list is stored in memory. The scatter-gather DMA channel copies it as required into the main DMA registers. The format of the DMA list in memory is as follows (illustrated in Figure 1): Each page entry takes eight bytes. Therefore, the scatter-gather DMA count is always evenly divisible by eight. The first word consists of the 32-bit start address of a memory page. The most significant 16 bits of the second word contain control data.
PCI CD and PCI CDa Bit A31–0 Description The address of the current DMA or the last used address if no DMA is currently active. Main DMA Next Address Register Size 32-bit I/O read-only Address 0x04 + (channel number x 20 hex) Access EDT_DMA_NXT_ADDR Comments The scatter-gather DMA fills this register when required from the scattergather DMA list. Bit A31–0 Description Read the starting address of the next DMA.
PCI CD and PCI CDa Main DMA Next Count and Control Register Size 32-bit I/O read-only Address 0x0C Access EDT_DMA_NXT_CNT Comments The scatter-gather DMA fills this register when required from the scattergather DMA list. Bit Description A31–16 Read-only versions of bits 31–16 of the scatter-gather DMA next count and control register. D15–0 The number of words still to be transferred in the current DMA.
PCI CD and PCI CDa Scatter-gather DMA Next Address Register Size 32-bit I/O read-write Address 0x14 Access EDT_SG_NXT_ADDR Comments The driver software writes this register as described in step 2 of the list in the Performing DMA section on page 74. Bit A31–0 Description The starting address of the next DMA.
PCI CD and PCI CDa Scatter-gather DMA Next Count and Control Register Size 32-bit I/O read-write Address 0x1C Access EDT_SG_NXT_CNT Comments The driver software writes this register as described in step 2 of the list in the Performing DMA section on page 74. Bit Description D31 EN_RDY Enable scatter-gather next empty interrupt.
PCI CD and PCI CDa D24 BURST_EN A value of 0 means bytes are written to memory as soon as they are received. A value of 1 means bytes are saved to write the most efficient number at once. D23 MN_DMA_DONE Read only: a value of 1 indicates that the main DMA is not active. D22 MN_NXT_EMP Read only: a value of 1 indicates that the main DMA next address and next count registers are empty. Reserved for EDT internal use.
PCI CD and PCI CDa D24 A value of 1 causes the data in the flash ROM data register to be written to the address specified by bits 0 through 23. A value of 0 reads the data. D23-0 Address of location in flash ROM that the next read or write will access.
PCI CD and PCI CDa Interrupt Registers PCI Interrupt and Remote Xilinx Configuration Register Size 32-bit I/O read-write Address 0xC4 Access EDT_REMOTE_OFFSET Comment Remote Xilinx is also referred to as Interface or User Xilinx. Bit EDT_ D31–22 Description Not used. D21 RMT_STATE Remote Xilinx INIT pin state. This bit is read-only. D20 RMT_DONE Remote Xilinx DONE pin. D19 RMT_PROG Remote Xilinx PROG pin. D18 RMT_INIT Remote Xilinx INIT pin.
PCI CD and PCI CDa The programming has failed if it has not completed after 32 clock cycles. PCI Interrupt Status Register Size 32-bit I/O read-only Address 0xC8 Access EDT_DMA_STATUS Comments The driver uses this register initially to determine the source of a PCI interrupt. Bit EDT_ D16–31 D15 Description Not used. PCI_INTR D14 PCI interrupt. When asserted, the PCI CD is asserting an interrupt on the PCI bus. Not used. D13 RMT_INTR Remote Xilinx interrupt.
PCI CD and PCI CDa Command Register Size 8-bit I/O read-write Address 0x00 Access PCD_CMD Bit Description D0 DIR A value of 1 indicates data is coming in to the PCI CD. D1 FORCEBNR A value of 1 tells device that board is not ready. D2 DATA_INV If this bit is set, the PCI CD inverts the data. D3 ENABLE Set to 1 to enable the PCI CD interface. This bit is set after the direction is chosen and typically after the first DMA buffer is ready.
PCI CD and PCI CDa Data Path Status Register Size 8-bit I/O read-only Address 0x01 Access PCD_DATA_PATH_STAT Bit EDT_ Description D0 OF_NOT_EMP If this bit is set, the output FIFO is not empty. D1 IF_NOT_EMP If this bit is set, the input FIFO is not empty. D2 UNDERFLOW If the DNR signal is low and the ODV signal goes low because the output FIFO runs out of data, this bit is asserted and remains so throughout the data transfer. Reset this bit with the ENABLE bit in the Command register.
PCI CD and PCI CDa Stat Register Size 8-bit I/O read-only Address 0x03 Access PCD_STAT Bit PCD_ Description D0-3 STAT The state of user-definable STAT input signals as last sampled by the RXT clock signal. D4-7 STAT_INT Interrupt bits for the status bits.
PCI CD and PCI CDa Stat Polarity Register Size 8-bit I/O read-write Address 0x04 Access PCD_STAT_POLARITY Bit Description D0-3 POLARITY A value of 0 indicates that a change from 0 to 1 from one clock cycle to the next causes an interrupt in the corresponding bit of the STAT_INT register, if the corresponding bit is also enabled in STAT_INT_EN. A value of 1 causes the same event when the STAT_INT bit changes from 1 to 0 from one clock cycle to the next.
PCI CD and PCI CDa Direction Control Registers Size 8-bit each I/O read-write Address A at 0x06, B at 0x07 Access PCD_DIRA and PCD_DIRB Comments These registers determine whether the physical drivers or receivers on the interface are inputs or outputs. Each pin on the PCI CD can be programmed as either an input or an output. Pins are normally configured for inputs or outputs as documented in the connector pinout shown on page 65.
PCI CD and PCI CDa Programmed I/O Low Register Size 8-bit I/O read-write Address 0x08 Access PCD_PIO_OUTLO Bit PCD_ 7–0 Description Outputs data on the low 8 bits of the 16-bit word. Programmed I/O High Register Size 8-bit I/O read-write Address 0x09 Access PCD_PIO_OUTHI Bit PCD_ 7–0 Description Outputs data on the high 8 bits of the 16-bit word.
PCI CD and PCI CDa ragged ODV on start and underflows. 5 SETDNR A value of 1 stops transfer to device as if device set to DNR. 6 PIOEN A value of 1 translates DMA channel buffers and enables programmed I/O registers at 8 and 9. A write to 9 generates a 1 clock inside ODV. 7 SETIDV Set input data valid (used for debug).
PCI CD and PCI CDa Output Data Valid Delay Register (PCI CDa only) Size 8-bit I/O read-write Address 0x28 Access ODV_DELAY Bit 7-0 Name ODV_DELAY Description Set this register to the number of 16-bit words to hold off output. Outgoing data backs up in FIFO, reducing or eliminating ODV transitioning on start up.
PCI CD and PCI CDa Specifications PCI Bus Compliance Number of Slots 1 Transfer Size PCI CD: Maximum 64 bytes per transfer PCI CDa: Maximum 1024 bytes per transfer DVMA master Yes PCI Bus memory space Approximately 66 KB Clock Rate PCI CD: 33 MHz PCI CDa: 66 MHz Device Data Transfer Protocol Synchronous stream Buffers Application specific Software Drivers for Solaris 2.6+ (Intel and SPARC platforms), Windows NT/2000/XP Version 4.0, AIX Version 4.3, Irex 6.5, and Linux Red Hat Version 5.
