Specifications

103
3706C–MICRO–2/11
AT89LP3240/6440
Notes:1.Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.
2. Enable the master SPI prior to the slave device.
3. Slave echoes master on the next Tx if not loaded with new data.
SPR0
SPR1
SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no
effect on the slave. The relationship b
etween SCK and the oscillator frequency, F
OSC.
, is as follows:
SPR1
SPR0 SCK (TSCK = 0) SCK (TSCK = 1)
00f
OSC
/4 f
T1OVF
/4
01f
OSC
/8 f
T1OVF
/8
10f
OSC
/32 f
T1OVF
/32
11f
OSC
/64 f
T1OVF
/64
Symbol Function
Table 17-3. SPDR – SPI Data Regis ter
SPDR Address = EAH
Reset Value= 00H (after cold reset)
unchanged (after warm reset)
Not Bit Addressable
SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Bit76543210
Table 17-4. SPSR – SPI Status Register
SPSR Address = E8H Reset Value = 0000 X000B
Not Bit Addressable
SPIF WCOL
MODF TXE – SSIG DISSOENH
Bit76543210
Symbol Function
SPIF
SPI Transfer Complete Interrupt Flag. When a serial transfer is complete, the SPIF bit is set by hardware and an interrupt
is generated if ESP = 1. The SPIF bit may be cleared by software or by reading the SPI status register followed by
reading/writing the SPI data register.
WCOL
Write Collision Fla
g. The WCOL bit is set by hardware if SPDR is written while the transmit buffer is full. The ongoing
transfer is not affected. WCOL may be cleared by software or by reading the SPI status register followed by
reading/writing the SPI data register.
MODF
Mode Fault Flag. MODF is set by hardware when a master mode collision is detected (MSTR = 1,
SSIG = 0 and SS = 0)
and an interrupt is generated if ESP= 1. MODF must be cleared by software.
TXE
Transmit Buffer Empty Flag. Set by hardware when the transmit buffer is loaded into the shift register, allowing a new byte
to be loaded. TXE must be cleared by software. When ENH = 1 and ESP = 1, TXE will generate an interrupt.