Specifications

104
3706C–MICRO–2/11
AT89LP3240/6440
17.4 Serial Clock Timing
The CPHA, CPOL and SPR bits in SPCR control the shape and rate of SCK. The two SPR bits
provide four possible clock rates when the SPI is in master mode. In slave mode, the SPI will
operate at the rate of the incoming SCK as long as it does not exceed the maximum bit rate.
There are a lso four possible combinations of SCK phase and polarity with respect to the
serial
data. CPHA and CPOL determine which format is used for transmission. The SPI data transfer
formats are shown in Figures 17-3 and 17-4. To prevent glitches on SCK from disrupting the
interface, CPHA, CPOL, and SPR should not be modified while the interface is enabled, and the
master device should be enabled before the slave device(s).
Figure 17-3.
SPI Transfer Format with CPHA = 0
Note: *Not defined but normally MSB of character just received.
Figure 17-4. SPI Transfer Format with CPHA = 1
Note: *Not defined but normally LSB of previously transmitted character.
SSIG
Slave Select Ignore. If SSIG = 0, the SPI will only operate in slave mode if SS
(P1.4) is pulled low. When SSIG = 1, the
SPI ignores SS in slave mode and is active whenever SPE (SPCR.6) is set. When MSTR = 1 and SSIG = 0, SS is
monitored for master mode collisions. Setting SSIG = 1 will ignore collisions on SS. P1.4 may be used as a regular I/O
pin when SSIG = 1.
DISSO
Disable slave output bit. When set, this bit causes the MISO pin to be tristated so that more than one slave device can
share the same interface without multiple SS
lines. Normally, the first byte in a transmission could be the slave address
and only the selected slave should clear its DISSO bit.
ENH
TX Buffer Interrupt Enable. When ENH = 1, TXE will generate an SPI interrupt if ESP = 1. When ENH = 0, TXE does not
generate an interrupt.
MSB 6 5 4 3 2
1 LSB
1 2 3 4 5 6 7 8
MSB
*
65432
1 LSB
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SS (TO SLAVE)