Specifications

105
3706C–MICRO–2/11
AT89LP3240/6440
18. Two-Wire Serial Interface
The Two-Wire Interface (TWI) is a bi-directional 2-wire serial communication standard. It is
designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised
of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs
connected to them. The only external hardware needed to implement the bus is a single pull-up
resistor for e
ach of the TWI bus lines. All devices connected to the bus have individual
addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. The
serial data transfer is limited to 400Kbit/s in standard mode. Various communication configura-
tions can be designed using this bus. Figure 18-1 shows a typical 2-wire bus config
uration. Any
of the devices connected to the bus can be master or slave.
The Two-Wire Interface on the AT89LP provides the following features:
• Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
• Both Master and Slave Operation Supported
•Device can Operate as Transmitter or Receiver
•7-bit Address Space Allows up to 128 Different Slave Addresses
•Multi-mas
ter Arbitration Support
• Up to 400 kHz Data Transfer Speed
•Fully Programmable Slave Address with General Call Support
Figure 18-1. Two-Wire Bus Configuration
As depicted in Figure 18-1, both bus lines are connected to the positive supply voltage through
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a
wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tristate their outputs, allowing the pull-up resistors to pull the line
high. Note that all AT89LP devices connected to the TWI bus must be powered in order to allow
any bus operation. The number of devices that can be connected to the bus
is only limited by the
bus capacitance limit of 400 pF and the 7-bit slave address space.
Device 1
Device 2
Device 3
Device n
SDA
SCL
........
R1 R2
V
CC