Specifications

106
3706C–MICRO–2/11
AT89LP3240/6440
18.1 Data Transfer and Frame Format
18.1.1 Transferring Bits
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 18-2. Data Validity
18.1.2 START and STOP Conditions
The Master initiates and terminates a data transmission. The trans
mission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
other Master should try to seize control of the bus. A special case occurs when a new START
condition is issued between a START and STOP condition. This is referred to as
a REPEATED
START condition, and is used when the Master wishes to initiate a new transfer without relin-
quishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the remainder of this data sheet, unless otherwise noted.
As depicted b
elow, START and STOP conditions are signalled by changing the level of the SDA
line when the SCL line is high.
Figure 18-3. START, REPEATED START, and STOP Conditions
18.1.3 Address Packet Format
All address packets transmitted on the TWI bus are nine bits long, consisting of seven address
bits, one READ/WRITE
control bit and an acknowledge bit. If the READ/WRITE bit is set, a read
operation is to be performed, otherwise a write operation should be performed. When a slave
recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL
(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas-
SDA
SCL
Data Stable Data Stable
Data Change
SDA
SCL
START STOPREPEATED STARTSTOP START