Specifications

109
3706C–MICRO–2/11
AT89LP3240/6440
Figure 18-7. SCL Synchronization between Multiple Masters
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the master had output, it has
lost the arbitration. Note that a master can only lose arbitration when it ou
tputs a high SDA value
while another master outputs a low value. The losing master should immediately go to Slave
mode, checking if it is being addressed by the winning master. The SDA line should be left high,
but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitr
ation will continue until only one master remains, and this may take many
bits. If several masters are trying to address the same slave, arbitration will continue into the
data packet.
Figure 18-8. Arbitration between Two Masters
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit.
•A
STOP condition and a data bit.
• A REPEATED STA RT and a STOP condition.
TA
low
TA
high
SCL from
Master A
SCL from
Master B
SCL bus
Line
TB
low
TB
high
Masters Start
Counting Low Period
Masters Start
Counting High Period
SDA from
Master A
SDA from
M
SDA Line
Synchronized
SCL Line
START
Master A Loses
Arbitration, SDA
A
SDA