Specifications

115
3706C–MICRO–2/11
AT89LP3240/6440
long as the TWIF bit in TWCR is set. Immediately after the application has cleared
TWIF, the TWI will initiate transmission of the data packet.
6. When the data packet has been transmitted, the TWIF flag in TWCR is set, and TWSR
is updated with a status code indicating that the data packet has successfully been
sent. The sta
tus code will also reflect whether a slave acknowledged the pa cket or not.
7. The application software should now examine the value of TWSR, to make sure that the
data packet was successfully transmitted, and that the value of the ACK bit was as
expected. If TWSR indicates otherwise, the application software might take some spe-
ci
al action, like calling an error routine. Assuming that the status code is as expected,
the application must write a specific value to TWCR, instructing the TWI hardware to
transmit a STOP condition. Which value to write is described later on. However, it is
important that the TWIF bit is cleared in the value written. The TWI will not start any
operation as long as the TWIF bit in TWCR is
set. Immediately after the application has
cleared TWIF, the TWI will initiate transmission of the STOP condition. Note that TWIF
is NOT set after a STOP condition has b een sent.
Even though this example is simple, it shows the principles involved in all TWI transmissions.
These can be summarized as follows:
• When the TWI has finished an operation and expects a
pplication response, the TWIF flag is
set. The SCL line is pulled low until TWIF is cleared.
• When the TWIF flag is set, the user must update all TWI registers with the value relevant for
the next TWI bus cycle. As an example, TWDR must be loaded with the value to be
transmitted in the next bus cycle.
•After all TWI Register updates and other pending application software t
asks have been
completed, TWCR is written. When writing TWCR, the TWIF bit should be cleared. The TWI
will then commence executing whatever operation was specified by the TWCR setting.
18.6 Transmission Modes
The TWI can operate in one of fou r major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be used in the same application. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system,
some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possib le status codes are described
along with figures detailing data transmiss ion in each of the modes. These figu
res contain the
following abbreviations:
S: START condition
Rs: REPEATED START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A
: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition