Specifications

119
3706C–MICRO–2/11
AT89LP3240/6440
TWEN must be written to one to enable the Two-wire Serial Interface, STA must be written to
one to transmit a START condition and TWIF must be cleared. The TWI will then test the Two-
wire Serial Bus and generate a START condition as soon as the bus becomes free. After a
START condition has been transmitted, the TWIF flag is set by hardware, and the status code in
TWSR will be 0
8h (see Table 18-7). In order to enter MR mode, SLA+R must be transmitted.
This is done by writing SLA+R to TWDR. Thereafter the TWIF bit should be cleared to continue
the transfer.
When SLA+R has been transmitted and an acknowledgment bit has been received, TWIF is set
aga in and a number of status codes in TWSR are possi
ble. Possible status codes in Master
mode are 38h, 40h or 48h. The appropriate action to be taken for each of these status codes is
detailed in Table 18-7. Received data can be read from the TWDR Register when the TWIF flag
is set high by hardware. This scheme is repeated until the last byte has been received. After the
last
byte has been received, the MR should inform the ST by sending a NACK after the last
received data byte. The transfer is ended by generating a STOP condition or a repeated START
condition.
Table 18-7. Status Codes for Master Receiver Mode
Status
Code
(TWSR)
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface Hardware
Application Software Response
Next Action Taken by TWI HardwareTo/from TWDR
To TWCR
STA STO TWIF AA
08h
A START condition has
been transmitted
Load SLA+R 0 0 1 X
SLA+R will be transmitted; ACK or NOT ACK
will be received
10h
A repeated STA RT
condition has been
transmitted
Load SLA+R 0 0 1 X
SLA+R will be transmitted; ACK or NOT ACK
will be received
Load SLA+W 0 0 1 X
SLA+W will be transmitted; Logic will switch to
Master Transmitter mode
38h
Arbitra
tion lost in SLA+R or
NOT ACK bit
No action 0 0 1 X
Two -w ire Serial Bus will be released and not
addressed Slave mode will be entered
No action 1 0 1 X
A START condition will be transmitted when the
bus becomes free
40h
SLA+R has been
transmitted; ACK has been
received
No action 0 0 1 0
Data byte will be received and NOT ACK will be
returned
No action 0 0 1 1
Data byte will be received a
nd ACK will be
returned
48h
SLA+R has been
transmitted; NOT ACK has
been received
No action 1 0 1 X Repeated START will be transmitted
No action 0 1 1 X
STOP condition will be transmitted and S TO
flag will be reset
No action 1 1 1 X
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
50h
Data byte has been
received; ACK has
been
returned
Read data byte 0 0 1 0
Data byte will be received and NOT ACK will be
returned
Read data byte 0 0 1 1
Data byte will be received and ACK will be
returned
58h
Data byte has been
received; NOT ACK has
been returned
Read data byte 1 0 1 X Repeated START will be transmitted
Read dat
a byte 0 1 1 X
STOP condition will be transmitted and S TO
flag will be reset
Read data byte 1 1 1 X
STOP condition followed by a START condition
will be transmitted and STO flag will be reset