Specifications

134
3706C–MICRO–2/11
AT89LP3240/6440
Figure 20-1. DADC Block Diagram
Table 20-1. Example ADC Conversion Codes
Right Adjust Left Adjust Single-Ended Mode (VIN) Differential Mode (VIN+ – VIN-)
00 V
DD/2 0
0100h 4000h V
DD/2 + 1/2 x VREF 1/2 x VREF
01FFh 7FC0h VDD/2 + 511/512 x VREF 511/512 x VREF
FF00h C000h VDD/2 – 1/2 x VREF –1/2 x VREF
FE01h 8040h VDD/2 – 511/512 x VREF –511/512 x VREF
8-BIT DATA BUS
15 0
ADC INPUT SELECT
REGISTER (DADI)
ADC CTRL & STATUS
REGISTER (DADC)
ADC DATA REGISTER
(DADH/DADL)
ACS2
DAC
ADIF
ACS1
ACS0
ACK0
ACK1
ACK2
DIFF
10-BIT SAR
SAMPLE &
HOLD
INTERNAL
1.0V
REFERENCE
ACON
VDD
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
IREF
+
-
CHANNEL SELECTION
PRESCALER
GND
POS.
INPUT
MUX
NEG.
INPUT
MUX
TRIGGER
SELECT
Timer
Overflows
INTERRUPT
FLAG
START
AVDD/2
DA+
DA-
TRG1
TRG0
GO
ADCE
LADJ
VREF
VIN+
VIN-
R
R
VDD/2