Specifications

137
3706C–MICRO–2/11
AT89LP3240/6440
Figure 20-5. Equivalent Analog Output Model
20.3 Clock Selection
The DADC requires a clock of 2 MHz or less to achieve full resolution. By default the DADC will
use an internal 2 MHz clock generated from the 8 MHz internal oscillator. The internal oscilla tor
will be enabled even if it is not supplying the system clock. This may result in higher power con-
sumption. Conversely, the DADC clock can be generated directly from the system clock using a
7-bit prescaler. The presca ler output is controlled by the ACK bits in DADC as
shown in Figure
20-6.
In ADC mode, there are no requirements on the clock frequency with respect to the system
clock. The ADC prescaler selection is independent of the system clock divider and the ADC may
operate at both higher or lower frequencies than the CPU. However, in DAC mode the ADC
clock frequency must not be higher than the CPU clock, including any clock division from the
system clock.
Figure 20-6. DADC Clock Selection
20.4 Starting a Conversion
Setting the GO/BSY bit (DADC.6) when ADCE = 1 starts a single conversion in both ADC and
DAC modes. The bit remains set while the conversion is in progress and is cleared by hardware
when the conversion completes. The ADC channel should not be changed while a conversion is
in progress.
Alternatively, a convers ion can be sta rted automatically by various timer
sources. Conversion
trigger sources are selected by the TRG bits in DADI. A conversion is started every time the
selected timer overflows, allowing for conversions to occur at fixed intervals. The GO/BSY bit will
DAn
V
OUT
R
OUT
=
100 kΩ
C
PIN
=
10 pF
AV
DD
/2
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ACK0
ACK1
ACK2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
INTERNAL
8MHz OSC
÷ 4