Specifications

138
3706C–MICRO–2/11
AT89LP3240/6440
be set by hardware while the conversion is in progress. Note that the timer overflow rate must be
slower than the conversion time.
20.5 Noise Considerations
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
• Connect a decoupling capacitor between the V
DD pin and GND as shown in Figure 20-7. This
capacitor should be located as close to the package as possible.
• Keep analog signal paths as short as possible. Make sure to run analog signals tracks over
an analog ground plane, and keep them well away from high-speed digit
al tracks.
•Place the CPU in Idle during a conversion.
•If any Port 0 pins are used as digital outputs, it is essential that these do not switch while a
conversion is in progress.
Figure 20-7. Example ADC Power Connections (TQFP Package)
Analog Ground
Plane
P0.7 (ADC7)
34 35 36 37 38 39
33
32
31
30
29
28
P0.6 (ADC6)
P0.5 (ADC5)
P0.4 (ADC4)
P0.3 (ADC3)
P0.2 (ADC2) P0.1 (ADC1) P0.0 (ADC0) VDD VDD
GND
100
nF