Specifications

139
3706C–MICRO–2/11
AT89LP3240/6440
Table 20-2. DADC – DADC Control Register
DADC = D9H Reset Value = 0000 0000B
Not Bit Addressable
ADIF GO/BSY
DAC ADCE LADJ ACK2 ACK1 ACK0
Bit76543210
Symbol Function
ADIF ADC Interrupt Flag. Set by hardware when a conversion completes. Cleared by hardware when calling the interru pt
service routine.
GO/BSYConversion Start/Busy Flag. In software triggered mode, writing a 1 to this bit starts a conversion. The bit remains high
while the conversion is in progress and is cleared by hardware when the conversion completes. In hardwa
re triggered
mode, this bit is set and cleared by hardware to flag when the DADC is busy.
DAC Digital-to-Analog Conversion Enab le. Set to configure the DADC in Digital-to-Analog (DAC) mode. Clear to configure the
DADC in Analog-to-Digital (ADC) mode.
ADCE DADC Enable. Set to enable the DADC. Clear to disable the DADC.
LADJ Left Adjust Enable. When cleared, the ADC results are right adjusted and the MSBs are sign extended. When set, the
ADC results are left adj
usted and the LSBs are zeroed.
ACK [2-0] DADC Clock Select
ACK3 ACK1 ACK0 Clock Source
000Internal RC Oscillator/4 (2MHz)
001f
sys
/2
010f
sys
/4
011f
sys
/8
100f
sys
/16
101f
sys
/32
110f
sys
/64
111f
sys
/128
Table 20-3. DADL – DADC Data Low Register
DADL = DCH Reset Value = 0000 0000B
Not Bit Addressable
ADC.7 ADC.6
ADC.5 ADC.4 ADC.3 ADC.2 ADC.1 ADC.0
Bit76543210
Table 20-4. DADH – DADC Data High Register
DADH = DDH Reset Value = 0000 0000B
Not Bit Addressable
ADC.15 ADC.14
ADC.13 ADC.12 ADC.11 ADC.10 ADC.9 ADC.8
Bit76543210