Specifications

14
3706C–MICRO–2/11
AT89LP3240/6440
Some internal data memory s paces are mapped into portions of the XDATA address space. In
this case the lower address ranges will access internal resources instead of external memory.
Addresses above the range implemented internally will default to XDATA. The
AT89LP3240/6440 supports up to 52K or 60K bytes of external memory when using the inter-
nally mapped memories. Setting the EXRAM bit (AUXR.1) to one will force a
ll MOVX
instructions to access the entire 64KB XDATA regardless of their address (See “AUXR – Auxil-
iary Control Register” on page 18).
3.3.2 EDATA
The Extra RAM is a portion of the external memory space implemented as an internal 4K byte
auxiliary RAM. The Extra RAM is mapped into the EDATA space at the bottom of the external
memory address space, from 0000H to 0FFFH. MOVX instructions to this address range will
acce
ss the internal Extra RAM. EDATA can be accessed with both 16-bit (MOVX @DPTR) and
8-bit (MOVX @Ri) addresses. When 8-bit a ddresses are used, the PAGE register (086H) sup-
plies the upper address bits. The PAGE register breaks EDATA into sixteen 256-byte pages. A
page cannot be specified independently for MOVX @R0 and MOVX @R1. Setting PAGE above
0FH enables XDATA acce
ss, but does not change the value of Port 2. When 16-bit addresses
are used (DPTR), the IAP bit (MEMCON.7) must be zero to access EDATA. MOVX instructions
to EDATA require a minimum of 2 clock cycles.
3.3.3 FDATA
The Flash Data Memory is a portion of the external memory space implemented as an internal
nonvolatile data memory. Flash Data Memory is enabled by setting the DMEN bit (MEMCON.3)
to one. When IAP = 0 and DMEN = 1, the Flash Dat
a Memory is mapped into the FDATA space,
directly above the EDATA space near the bottom of the external memory address space, from
1000H to 2FFFH. (See Figure 3-3). MOVX instructions to this address range will access the
internal nonvolatile memory. FDATA is not accessible while DMEN = 0. FDATA can be
accessed only by 16-bit (MOVX @DPTR) addresses. MOVX @Ri instructions to the FDATA
address range will acce
ss external memory. Addresses above the FDATA range are mapped to
XDATA. MOVX instructions to FDATA require a minimum of 4 clock cycles.
3.3.3.1 Write Protocol
The FDATA address space a ccesses a n internal nonvola tile data memory. This address space
can be read just like EDATA by issuing a MOVX A,@DPTR; however, writes to FDATA require a
more complex protocol and take several milliseconds to complete. The AT8
9LP3240/6440 uses
an idle-while-write architecture where the CPU is placed in an idle state while the write occurs .
When the write completes, the CPU will continue executing with the instruction after the
MOVX @DPTR,A instruction that started the write. All peripherals will continue to function during
the write cycle; however, interrupts will not be serviced until the write completes.
Table 3-2.
PAG E – EDATA Page Register
PAG E = 86H Reset Value = 0000 0000B
Not Bit Addressable
PAGE.7 PAGE.6 PAGE.5 PAGE.4 PAGE.3 PAGE.2 PAGE.1 PAGE.0
Bit76543210
Symbol Function
PAG E
7-0
Selects which 256-byte page of EDATA is currently accessible by MOVX @Ri instructions when PAGE < 10H. Any PAGE
value between 10H and FFH will selected XDATA; however, this value will not be output on P2.