Specifications

144
3706C–MICRO–2/11
AT89LP3240/6440
INC /DPTR
(1)
2– 3A5 A3
MUL AB 1 48 2A4
DIV AB 1 48 4 84
DA A 1 12 1 D4
MAC AB
(1)
2– 9A5 A4
CLR M
(1)
2– 2A5 E4
ASR M
(1)
2– 2A5 03
LSL M
(1)
2– 2A5 23
Bit Operations Bytes
Clock Cycles
Hex Code8051 AT89LP
CLR C 1 12 1 C3
CLR bit 2 12 2 C2
SETB C 1 12 1 D3
SETB bit 2 12 2 D2
CPL C 1 12 1 B3
CPL bit 2 12 2 B2
ANL C, bit 2 24 2 82
ANL C, bit 2 24 2 B0
ORL C, bit 2 24 2 72
ORL C, /bit 2 24 2 A0
MOV C, bit 2 12 2 A2
MOV bit, C 2 24 2 92
Logical Bytes
Clock Cycles
Hex Code8051 AT89LP
CLR A 1 12 1 E4
CPL A 1 12 1 F4
ANL A, Rn 1 12 1 58-5F
ANL A, direct 2 12 2 55
ANL A, @Ri 1 12 2 56-57
ANL A, #data 212 2 54
ANL direct, A 2 12 2 52
ANL direct, #data 324 3 53
ORL A, Rn 1 12 1 48-4F
ORL A, direct 2 12 2 45
ORL A, @Ri 1 12 2 46-47
ORL A, #data 212 2 44
ORL direct, A 2 12 2 42
ORL direct, #data 324 3 43
XRL A, Rn 1 12 1 68-6F
Table 22-1. Instruction Execution Times and Exceptions (Continued)