Specifications

146
3706C–MICRO–2/11
AT89LP3240/6440
Notes:1.This escaped instruction is an extension to the instruction set. See Section 22.1 on page 147.
2. MOVX @DPTR instructions take 2 clock cycles when accessing ERAM and 4 clock cycles
when accessing FDATA, XDATA or CODE. (3 and 5 cycles for MOVX @/DPTR).
3. The BREAK instruction acts as a 2 cycle NOP.
4. Instructions accessing the stack require additional cycles when using the extended sta
ck.
POP direct 2 24 2/3
(4)
D0
XCH A, Rn 1 12 1 C8-CF
XCH A, direct 2 12 2 C5
XCH A, @Ri 1 12 2 C6-C7
XCHD A, @Ri 1 12 2 D6-D7
Branching Bytes
Clock Cycles
Hex Code8051 AT89LP
JC rel 2 24 3 40
JNC rel 2 24 3 50
JB bit, rel 3 24 4 20
JNB bit, rel 3 24 4 30
JBC bit, rel 3 24 4 10
JZ rel 2 24 3 60
JNZ rel 2 24 3 70
SJMP rel 2 24 3 80
ACALL addr11 2 24 3/5
(4)
11,31,51,71,91,
B1,D1,F1
LCALL addr16 3 24 4/6
(4)
12
RET 1 24 4/5
(4)
22
RETI 1 24 4/5
(4)
32
AJMP addr11 2 24 3
01,21,41,61,81,
A1,C1,E1
LJMP addr16 3 24 4 02
JMP @A+DPTR 1 24 2 73
JMP @A+PC
(1)
2– 3A573
CJNE A, direct, rel 3 24 4 B5
CJNE A, #data, rel 3 24 4 B4
CJNE Rn, #data, rel 3 24 4 B8-BF
CJNE @Ri, #data, rel 3 24 4 B6-B7
CJNE A, @R0, rel
(1)
3– 4A5 B6
CJNE A, @R1, rel
(1)
3– 4A5 B7
DJNZ Rn, rel 2 24 3 D8-DF
DJNZ direct, rel 3 24 4 D5
NOP 1 12 1 00
BREAK
(1)(3)
2– 2A500
Table 22-1. Instruction Execution Times and Exceptions (Continued)