Specifications

147
3706C–MICRO–2/11
AT89LP3240/6440
22.1 Instruction Set Extensions
The following instructions are extensions to the standard 8051 instruction set that provide
enhanced capabilities not found in standard 8051 devices. All extended instructions start with an
A5H escape code. For this reason random A5H reserved codes should not be placed in the
instruction stream even though other devices may ha
ve treated these as NOPs.
Other AT89LP devices may not support all of these instructions.
22.1.1 ASR M
Function: Shift MAC Accumulator Right Arithmetically
Description: The forty bits in the M register are shifted one bit to the right. Bit 39 retains its value to preserve the sign of the
value. No flags are affected.
Example: The M register holds the value 0C5B1A29384H . The following instruction,
ASR M
leaves the M register holding the value 0E2D8D149C2H.
Bytes: 2
Cycles: 2
Encoding: A5 00000011
Operation: ASR
(M
n
) ← (M
n + 1
) n = 0 - 38
(M
39
) ← (M
39
)
22.1.2 BREAK
Function: Software Breakpoint (Halt execution)
Description: BREAK transfers control from normal execution to the On-Chip Debug (OCD) handler if OCD is enabled. The PC
is left pointing to the following instruction. If OCD is disabled, BREAK acts as a double NOP. No flags are
affected.
Example: If On-Chip Debugging is allowed, the following instruction,
BREAK
will halt instruction execution prior to the immediately following instruction. If debugging is not allowed, the
BREAK is treated as a
double NOP.
Bytes: 2
Cycles: 2
Encoding: A5 00000000
Operation: BREAK
(PC) ← (PC) + 2