Specifications

155
3706C–MICRO–2/11
AT89LP3240/6440
24. On-Chip Debug System
The AT89LP3240/6440 On-Chip Debug (OCD) System uses a two-wire serial interface to con-
trol program flow; read, modify, and write the s ystem state; and program the nonvolatile
memory. The OCD System has the following features:
• Complete program flow control
•Read-Modify-Write access to all internal SFRs and data memories
•Four hardware program address breakpoints, plus fo
ur program/data address breakpoints
• Unlimited program software breakpoints using BREAK instruction
•Break on change in program memory flow
•Break on stack overflow/underflow
•Break on Watchdog overflow
•Break on reset
• Non-intrusive operation
•Programming of nonvolatile memory
24.1 Physical Interface
The On-Chip Debug System uses a two-wire synchronous serial interface to establish communi-
cation between the target device and the controlling emu lator system. The OCD interface is
enabled by clearing the OCD Enable
Fuse. The OCD device connections are shown in Figure
24-1. When OCD is enabled, the RST
port pin is configured as an input for the Debug Clock
(DCL). Either the XTAL1, XTAL2 or P4.3 pin is configu red as a bi-directional data line for the
Debug Data (DDA) depending on the clock source selected. If the Internal RC Oscillator is
selected, XTAL1 is configured as DDA (A).If the External Clock is selected, XTAL2 is configured
as DDA (B). If the Crystal Oscillator is selected, P4.3 is configured as DDA (C).
When designing a system where On-Chip Debug will be
used, the following observations must
be considered for correct operation:
TH0 8CH Table 11-1 on page 51
TH1 8DH Table 11-1 on page 51
TH2 CDH Section 12.1 on page 61
TL0 8AH Table 11-1 on page 51
TL1 8BH Table 11-1 on page 51
TL2 CCH Section 12.1 on page 61
TMOD 89H Table 11-3 on page 55
TWAR
ACH Table 18-3 on page 112
TWBR
AEH Table 18-5 on page 113
TWCR
AAH Table 18-1 on page 112
TWDR
ADH Table 18-4 on page 113
TWSR
ABH Table 18-2 on page 112
WDTCON
A7H Table 21-2 on page 142
WDTRST
A6H Table 21-3 on page 142
Table 23-1. Special Function Register Cross Reference