Specifications

159
3706C–MICRO–2/11
AT89LP3240/6440
•The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a
maximum frequency of 5 MHz.
•The AT89LP3240/6440 will enter programming mode only when its reset line (RST
) is
active (low). To simplify this operation, it is recommended that the target reset can be
controlled by the In-System programmer. To avoid problems, the In-System programmer
should be able to keep the entire target system reset for the duration of the programming
cycle. The target system should never attempt to drive the four SPI lines while reset is active.
•The RST
input may be disabled to gain an extra I/O pin. In these cases the RST pin will
always function as a reset during power up. To enter programming the RST
pin must be
driven low prior to the end of Power-On Reset (POR). After POR has completed the device
will remain in ISP mode until RST
is brought high. Once the initial ISP session has ended, the
power to the target device must be cycled OFF and ON to enter another session.
•The SS
pin should not be left floating during reset if ISP is enabled.
•The ISP Enable Fuse must be set to allow programming during any reset period. If the ISP
Fuse is disabled, ISP may only be entered at POR.
•For standalone programmers, RST
may be tied directly to GND to ensure correct entry into
Programming mode regardless of the device settings.
25.2 Memory Organization
The AT89LP3240/6440 offers 64K bytes of In-System Programmable (ISP) nonvolatile Flash
code memory and 8K bytes of nonvolatile Flash data memory. In addition, the device contains a
256-byte User Signature Array and a 128-byte read-only Atmel Signature Array. The memory
organization is shown in Table 25-1 and Figure 25-3. The memory is divided into page
s of 128
bytes each. A single read or write command may only access half a page (64 bytes) in the mem-
ory; however, write with auto-erase commands will erase an entire 128-byte pa ge even though
they can only write one half page. Each memory type resides in its own address space and is
accessed by commands specific to that memory. However, all memory types share the sa
me
page size.
User configuration fuses are mapped as a row in the memory, with each byte representing one
fuse. From a programming standpoint, fuses are treated the same as normal code bytes except
they are not affected by Chip Erase. Fuses can be enabled at any time by writing 00h to the
appropriate locations in the fuse row. However, to disable a fuse, i.e.
set it to FFh, the entire
fuse row must be erased and then reprogrammed. The programmer should read the state of all
the fuses into a temporary location, modify those fuses which need to be disabled, then issue a
Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a simi-
lar manner to fuses except they may only be erased (unlocked) b
y Chip Erase.
Table 25-1. AT89LP3240/6440 Memory Organization
Memory Capacity Page Size # Pages Address Range
CODE 32KB (AT89LP3240) 128 bytes 256 0000H – 7FFFH
64KB (AT89LP6440) 128 bytes 512 0000H – FFFFH
DATA 8192 bytes 128 bytes 64 1000H – 3FFFH
User Signature 256 bytes 128 bytes 2 0000H – 00FFH
Atmel Signature 128 bytes 128 bytes 1 0000H – 007FH