Specifications

167
3706C–MICRO–2/11
AT89LP3240/6440
Figure 25-9. In-System Programming (ISP) Start Sequence
25.9.4 ISP Exit Sequence
Execute this sequence to exit ISP mode and resume CPU execution mode.
1. Drive SCK low.
1. Wait at least t
SSD
and drive SS high.
2. Tristate MOSI.
3. Wait at least t
SSZ
and bring RST high.
4. Tristate SCK.
5. Wait t
RHZ
and tristate SS.
Figure 25-10. In-S ystem Programming (ISP) Exit Sequence
Note: The waveforms on this page are not to scale.
25.9.5 Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is a byte-oriented full-duplex synchronous serial communi-
cation channel. During In-System Programming, the programmer always acts as the SPI master
and the target device always acts as the SPI slave. The target device receives serial data on
MOSI a
nd outputs seria l data on MISO. The Programming Interfa ce implements a standard
SPI Port with a fixed data order and For In-System Programming, bytes are transferred MSB
first as shown in Figure 25-11. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0,
t
STL
V
DD
RST
SS
SCK
HIGH ZMOSI
HIGH ZMISO
XTAL1
t
RLZ
t
ZSS
t
SSE
V
DD
RST
SS
SCK
HIGH ZMOSI
HIGH ZMISO
XTAL1
t
SSZ
t
SSD
t
RHZ