Specifications

168
3706C–MICRO–2/11
AT89LP3240/6440
CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of
SCK. For more detailed timing information see Figure 25-12.
Figure 25-11. ISP Byte Sequence
Figure 25-12. Serial Programming Interface Timing
Figure 25-13. Parallel Programming Interface Timing
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
MOSI
MISO
SCK
Data Sampled
t
SR
t
SSE
t
SLSH
t
SOV
t
SF
t
SOX
t
SSD
t
SCK
t
SHSL
t
SOE
t
SOH
t
SIH
t
SIS
SS
SCK
MISO
MOSI
t
SR
t
SSE
t
SLSH
t
SF
t
POX
t
SSD
t
SCK
t
SHSL
t
POV
t
POE
t
PIH
t
PIS
SS
SCK
P0
OE
t
POH