Specifications

169
3706C–MICRO–2/11
AT89LP3240/6440
25.9.6 Timing Parameters
The timing parameters for Figure 25-7, Figure 25-8, Figure 25-9, Figure 25-10, Figure 25-12 and
Figure 25-13 are shown in Table .
Note: 1. t
SCK
is independent of t
CLCL
.
Table 25-7. Programming Interface Timing Parameters
Symbol Parameter Min Max Units
t
CLCL
System Clock Cycle Time 0 60 ns
t
PWRUP
Power On to SS High Time 10 µs
t
POR
Power-on Reset Time 100 µs
t
PWRDN
SS Tr i state to Power Off 1 µs
t
RLZ
RST Low to I/O Tristate t
CLCL
2 t
CLCL
ns
t
STL
RST Low Settling Time 100 ns
t
RHZ
RST High to SS Tr i state 0 2 t
CLCL
ns
t
SCK
Serial Clock Cycle Time 200
(1)
ns
t
SHSL
Clock High Time 75 ns
t
SLSH
Clock Low Time 50 ns
t
SR
Rise Time 25 ns
t
SF
Fall Time 25 ns
t
SIS
Serial Input Setup Time 10 ns
t
SIH
Serial Input Hold Time 10 ns
t
SOH
Serial Output Hold Time 10 ns
t
SOV
Serial Output Valid Time 35 ns
t
PIS
Parallel Input Setup Time 10 ns
t
PIH
Parallel Input Hold Time 10 ns
t
POH
Parallel Output Hold Time 10 ns
t
POV
Parallel Output Va lid Time 35 ns
t
SOE
Serial Output Enable Time 10 ns
t
SOX
Serial Output Disable Time 25 ns
t
POE
Parallel Output Enable Time 10 ns
t
POX
Parallel Output Disable Time 25 ns
t
SSE
SS Enable Lead Time t
SLSH
ns
t
SSD
SS Disable Lag Time t
SLSH
ns
t
ZSS
SCK Setup to SS Low 25 ns
t
SSZ
SCK Hold after SS High 25 ns
t
WR
Write Cycle Time 2.5 ms
t
AWR
Write Cycle with Auto-Erase Time 5 ms
t
ERS
Chip Erase Cycle Time 7.5 ms