Specifications

183
3706C–MICRO–2/11
AT89LP3240/6440
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
Figure 26-21. Two-wire Serial Bus Timing
Figure 26-22. Shift Register Mode Timing Waveform
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r
26.10 Serial Port Timing: Shift Register Mode
The values in this table are valid for V
DD
= 2.4V to 3.6V and Load Capacitance = 80 pF.
Symbol Parameter
SMOD1 = 0 SMOD1 = 1
UnitsMin Max Min Max
t
XLXL
Serial Port Clock Cycle Time 4t
CLCL
-15 2t
CLCL
-15 µs
t
QVXH
Output Data Setup to Clock Rising Edge 3t
CLCL
-15 t
CLCL
-15 ns
t
XHQX
Output Data Hold after Clock Rising Edge t
CLCL
-15 t
CLCL
-15 ns
t
XHDX
Input Data Hold after Clock Rising Edge 0 0 ns
t
XHDV
Input Data Valid to Clock Rising Edge 15 15 ns
01234567
ValidValidValidValid Valid Valid Valid Valid
Clock
Write to SBUF
Output Data
Clear RI
Input Data
SMOD1 = 0
01234567
ValidValidValidValid Valid Valid Valid Valid
Clock
Write to SBUF
Output Data
Clear RI
Input Data
SMOD1 = 1