Specifications

19
3706C–MICRO–2/11
AT89LP3240/6440
automatically tristated when inputting data regardless of the Port 0 configuration. The Port 0
configuration will determine the idle state of Port 0 when not accessing the external memory.
Figure 3-9 and Figure 3-10 show examples of external data memory write and read cycles,
respectively. The address on P0 a nd P2 is stable at the falling edge of ALE. The idle polarity of
ALE is controlled by ALES (AUXR.0). When ALES = 0 the idle polarity of ALE is high (
active).
When ALES = 1 the idle polarity of ALE is low (inactive). The ALE strobe pulse is always active
high. Unlike standard 8051s, ALE will not toggle continuously when not accessing external
memory. ALES must be zero in order to use P4.4 as a general-purpos e I/O. The WS bits in
AUXR can extended the RD
and WR s trobes by 1, 2 or 3 cycles as shown in Figures 3-11, 3-12
and 3-13. If a longer strobe is required, the application can scale the system clock with the clock
divider to meet the requirements (See Section 6.5 on page 32).
Figure 3-9. External Data Memory Write Cycle (WS =00B)
Figure 3-10. External Data Memory Read Cycle (WS = 00B)
S1 S2 S3 S4
CLK
ALE
ALES = 0
ALES = 1
WR
DPL or Ri OUTP0 SFR P0 SFR
P0
P2 SFR P2 SFRDPH or P2 OUT
P2
DATA OUT
S1 S2 S3 S4
CLK
ALE
ALES = 0
ALES = 1
RD
FLOAT
DATA SAMPLED
DPL or Ri OUTP0 SFR P0 SFR
P0
P2 SFR P2 SFRDPH or P2 OUT
P2