Specifications

37
3706C–MICRO–2/11
AT89LP3240/6440
.
8.2 Power-down Mode
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator, disables the BOD and powers down the Flash memory in order to minimize power
consumption. Only the power-on circuitry will continue to draw power during Power-down. Dur-
ing Power-down, the power supply voltage may be reduced to the RAM keep-alive voltage. The
RAM contents will be retained, but the SFR contents are not guaranteed once V
DD
has been
reduced. Power-down may be exited by external reset, power-on reset, or certain enabled
interrupts.
8.2.1 Interrupt Recovery from Power-down
Three external interrupt sources may be configured to termina te Power-down mode: external
interrupts INT0
(P3.2) and INT1 (P3.3); and the general-purpose interrupts (GPI). To wake up by
external interrupt INT0
or INT1, that interrupt must be enabled by setting EX0 or EX1 in IE and
must be configured for level-sensitive operation by clearing IT0 or IT1. Any General-purpose
interrupt on Port 1 (GPI
7-0
) can also wake up the device. The GPI pin must be enabled in GPIEN
and configured for level-sensitive detection, and EGP in IE2 must be set in order to terminate
Power-down.
When terminating Power-down by an interru pt, two different wake-up modes are available.
When PWDEX in PCON is zero, the wake-up period is internally timed as shown in Figure 8-1.
At the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
begin. The time-ou t period is controlled by the Start-up Timer Fuses (see Table 7-1 on page 35).
The interrupt pin need not remain low for the entire time-out period.
Table 8-1.
PCON – Power Control Register
PCON = 87H Reset Value = 000X 0000B
Not Bit Addressable
SMOD1 SMOD0 PWDEX POF GF1 GF0 PD IDL
Bit76543210
Symbol Function
SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
SMOD0 Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
PWDEX Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 1, wake
up from Power-down is internally timed.
POF Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset
under software control and is not
affected by RST or BOD (i.e. warm resets).
GF1, GF0 General-purpose Flags
PD Power-down bit. Setting this bit activates power-down operation. The PD bit is cleared automa tically by hardware when
waking up from power-down.
IDL Idle Mode bit. Setting this bit activates Idle mode operation. The IDL bit is cleared automatically
by hardware when
waking up from idle