Specifications

42
3706C–MICRO–2/11
AT89LP3240/6440
rupt system, the response time is always more than 5 clock cycles and less than 21 clock cycles.
See Figure 9-1 a nd Figure 9-2.
Figure 9-1. Minimum Interrupt Response Time
Figure 9-2. Maximum Interrupt Response Time
.
Clock Cycles
INT0
IE0
15
Instruction LCALL 1st ISR Instr.Cur. Instr.
Ack.
Clock Cycles
INT0
IE0
1 21
Instruction RETI MAC AB LCALL 1st ISR Instr.
Ack.
615
Table 9-2. IE – Interrupt Enable Register
IE = A8H Reset Value = 0000 0000B
Bit Addressable
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit76543210
Symbol Function
EA Global enable/disable. All interrupts are disabled when EA = 0. When EA = 1, each interrupt source is enabled/disabled
by setting /clearing its own enable bit.
EC Comparator Interrupt Enable
ET2 Timer 2 Interrupt Enable
ESSerial Port Interrupt Enable
ET1 Timer 1 Interrupt Enable
EX1 External Interrupt 1 Enable
ET0 Timer 0 Interrupt Enable
EX0 Externa
l Interrupt 0 Enable