Specifications
45
3706C–MICRO–2/11
AT89LP3240/6440
10. I/O Ports
The AT89LP3240/6440 can be configured for between 35 and 38 I/O pins. The exact number of
I/O pins available depends on the clock and reset options as shown in Table 10-1.
10.1 Port Configuration
All port pins on the AT89LP3240/6440 may be configured to one of four modes: quasi-bidirec-
tional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port
modes may be assigned in software on a pin-by-pin basis as shown in Table 10-2 using the reg-
isters listed in Table 10-3. The Tristate-Port User Fus
e determines the default state of the port
pins. When the fuse is enabled, all port pins default to input-only mode after reset. When the
fuse is disabled, all port pins, with the exception of the analog inputs, P0.7-0, P2.4, P2.5, P2.6
and P2.7, default to quasi-bidirectional mode after reset and are weakly pulled high. The analog
input pins always reset to input-only (tristate) mode. Each port pin also has
a Schmitt-triggered
input for improved input nois e rejection. During Power-down all the Schmitt-triggered inputs a re
disabled with the exception of P3.2 (INT0
), P3.3 (INT1), P4.2 (RST), P4.0 (XTAL1) and P4.1
(XTAL2) which may be used to wake up the device. Therefore, P3.2, P3.3, P4.2, P4.0 and P4.1
should not be left floating during Power-down. In addition any pin of Port 1 configured as a Gen-
eral-Purpose interrupt input will also remain active during Power-down to wake-up the device.
These interrupt pins should either be disabled before entering Power-down or they should not be
left floating.
.
.
Table 10-1. I/O Pin Configurations
Clock Source Reset Option Number of I/O Pins
External Crystal or
Resonator
External RST
Pin 35
No external reset 36
External Clock
External RST
Pin 36
No external reset 37
Internal RC Oscillator
External RST Pin 37
No external reset 38
Table 10-2. Configuration Modes for Port x, Bit y
PxM0.y PxM1.y Port Mode
00Quasi-bidirectional
01Push-pull Output
10Input Only (High Impedance)
1 1 Open-Drain Output
Table 10-3. Port Configuration Registers
Port Port Data Port Configuration
0P0 (80H) P0M0 (BAH), P0M1 (BBH)
1 P1 (90H) P1M0 (C2H), P1M1 (C3H)
2 P2 (A0H) P2M0 (C4H), P2M1 (C5H)
3 P3 (B0H) P3M0 (C6H), P3M1 (C7H)
4 P4 (C0H) P4M0 (BEH), P4M1 (BFH)