Specifications

6
3706C–MICRO–2/11
AT89LP3240/6440
2. Overview
The AT89LP3240/6440 is a low-power, high-performance CMOS 8-bit microcontroller with
32K/64K b ytes of In-System Programmable Flash program memory and 8K bytes of Flash data
memory. The device is manufactured using Atmel
®
's high-density nonvolatile memory technol-
ogy and is compatible with the industry-standard 8051 instruction set. The AT89LP3240/6440 is
built around an enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to exe-
cute in 12, 24 or 48 clock cycles. In the AT89LP3240/6440 CPU, standard instructions need only
1 to 4 clock cycles
providing 6 to 12 times more throughput than the standa rd 8051. Seventy
percent of instructions need only as many clock cycles as they have bytes to execute, a nd most
of the remaining instructions require only one additional clock. The enhanced CPU core is capa-
ble of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same
current consumption. Conversely, at the sa
me throughput as the classic 8051, the new CPU
core runs at a much lower speed and thereby greatly reducing power consumption and EMI.
The AT89LP3240/6440 provides the following standard features: 32K/64K bytes of In-System
Programmable Flash program memory, 8K bytes of Flash data memory, 4352 bytes of RAM, up
to 38 I/O lines, three 16-bit timer/counters, up to
six PWM outputs, a programmable watchdog
timer, two ana log comparators, a 10-bit ADC/DAC with 8 input channels, a full-duplex serial port,
a serial peripheral interface, a two-wire serial interface, an internal RC oscillator, on-chip crystal
oscillator, and a four-level, twelve-vector interrupt system. A block diagra
m is shown in Figure 2-
1.
35 41 37 35 P0.2
I/O
O
I
P0.2: User-configurable I/O Port 0 bit 2.
AD2: External memory interface Address/Data bit 2.
ADC2: ADC analog input 2.
36 42 38 36 P0.1
I/O
O
I
P0.1: User-configurable I/O Port 0 bit 1.
AD1: External memory interface Address/Data bit 1.
ADC1: ADC analog input 1.
37 43 39 37 P0.0
I/O
O
I
P0.0: User-configurable I/O Port 0 bit 0.
AD0: External memory interface Address/Data b
it 0.
ADC0: ADC analog input 0.
38 44 40 38 VDD I Supply Voltage
39 1 39 VDD I Supply Voltage
40 2 1 40 P1.0
I/O
I/O
I
P1.0: User-configurable I/O Port 1 bit 0.
T2: Timer 2 External Input or Clock Output.
GPI0: General-purpose Interrupt input 0.
41 3 2 41 P1.1
I/O
I
I
P1.1: User-configurable I/O Port 1 bit 1.
T2EX: Timer 2 External Capture/Reload Input.
GPI1: General-purpose Interrupt input 1
42 4 3 42 P1.2
I/O
I
P1.2: U
ser-configurable I/O Port 1 bit 2.
GPI2: General-purpose Interrupt input 2.
43 5 4 43 P1.3
I/O
I
P1.3: User-configurable I/O Port 1 bit 3.
GPI3: General-purpose Interrupt input 3.
44 6 5 44 P1.4
I/O
I
I
P1.4: User-configurable I/O Port 1 bit 4.
SS
: SPI Slave-Select.
GPI6: General-purpose Interrupt input 4.
Table 1-1. AT89LP3240/6440 Pin Description
Pin Number
Symbol Type DescriptionTQFP PLCC PDIP VQFN