Specifications

3706C–MICRO–2/11

AT89LP3240/6440

registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer

underflows when TH2 and TL2 equal BOTTOM, the 16-bit value stored in RCAP2H and

RCAP2L. The underflow sets the TF2 bit and causes MAX to be reloaded into the timer regis-

ters. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th

bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

When T2EX = 1 a

nd T2CM

1-0

= 01B, the timer will overflow at TOP and set the TF2 bit. This

overflow also causes MIN to be reloaded into the timer registers. A logic 0 at T2EX makes Timer

2 count down. The timer underflows when TH2 and TL2 equal MIN. The underflow sets the TF2

bit and causes TOP to be reloaded into the timer registers. The behavior of Count Mode 0 ver-

sus Count Mode 0 when DCEN is enabled is shown in Figure 12-6.

Figure 12-4. Timer 2 Diagram: Auto-Reload Mode (T2CM

1-0

= 00B, DCEN = 1)

The timer overflow/underflow rate for up-down counting mode is the same as for up cou nting

mode, provided that the count direction does not change. Changes to the count direction may

result in longer or shorter periods between time-outs.

Figure 12-5. Timer 2 Diagram: Auto-Reload Mode (T2CM

1-0

= 01B, DCEN = 1)

÷TPS