Specifications

7
3706C–MICRO–2/11
AT89LP3240/6440
Timer 0 and Timer 1 in the AT89LP3240/6440 are enhanced with two new modes. Mode 0 can
be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit
auto-reload timer/counter. In addition, the timer/counters may each independently drive an 8-bit
precision pulse width modula tion output.
Timer 2 on the AT89LP3240/6440 serves as a 16-bit time base for a 4-channel Compare/C
ap-
ture Array with up to four multi-phasic, variable precision (up to 16-bit) PWM outputs.
The enhanced UART of the AT89LP3240/6440 includes Framing Error Detection and Automatic
Address Recognition. In addition, enhancements to Mode 0 allow hardware accelerated emula-
tion of half-duplex SPI or Two Wire interfaces.
The I/O ports of the AT89LP3240/6440 can be independently configured in one of four operating
modes. In quas
i-bidirectional mode, the ports operate as in the classic 8051. In input-only mode,
the ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode
provides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an inter-
rupt using the general-purpose interrupt interface.
2.1 Block Diagram
Figure 2-1. AT89LP3240/6440 Block Diagram
32K/64K Bytes
Flash Code
P o r t 2
Configu r a b le I/ O
P o r t 1
Configu r a b le I/ O
U A R T
SPI
Timer 0
Timer 1
Dual Analog
Comparators
W atchdo g
Timer
Internal
RC Oscillator
Gene r al-pu r pos e
Inter r up t
Configu r a b l e
Oscillator
C r ystal o r
Resonator
8K Bytes
Flash Data
P o r t 4
Configu r a b le I/ O
P o r t 3
Configu r a b le I/ O
Timer 2
Compare/
Capture Array
P o r t 0
Configu r a b le I/ O
TWI
8-channel 10-bit
ADC/DAC
8
256 Bytes
RAM
4K Bytes
ERAM
XRAM
Interface
8051 Single Cycle CPU
POR
BOD
Dual Data
Pointers
Multiply
Accumulate
(16 x 16)
On-Chip
Debug