Specifications

70
3706C–MICRO–2/11
AT89LP3240/6440
Figure 13-1. Compare/Capture Array Block Diagram
13.1 CCA Registers
The Compare/Capture Array has five Special Function Registers: T2CCA, T2CCC, T2CCL,
T2CCH and T2CCF. The T2CCF register contains the interrupt flags for each CCA channel. The
CCA interrupt is a logic OR of the bits in T2CCF. The flags are set by hardware when a com-
pare/capture event occurs on the relevant channel and must be cleared by software. The
T2CCF bits will only gener
ate an interrupt when the ECC bit (IE2.1) is set and the CIENx bit in
the associated channel’s CCCx register is set.
The T2CCC, T2CCL and T2CCH register locations are not true SFRs. These locations represent
access points to the contents of the array. Writes/reads to/from the T2CCC, T2CCL and T2CCH
locations will access the control, data low and data high byte
s of the CCA channel currently
selected by the index in T2CCA. Channels currently not indexed by T2CCA are not accessible.
When writing to T2CCH, the value is stored in a shadow register. When T2CCL is written, the
16-bit value formed by the contents of T2CCL and the T2CCH shadow is written into the array.
Therefore, T2CCH must be written prior to writing T2CCL. All four channels use the same
T2CCH shadow register. If the value of T2CCH remains consta
nt for multiple writes, there is no
need to update T2CCH between T2CCL writes. Every write to T2CCL will use the last value of
T2CCH for the upper data byte. It is not possible to write to the data register of a channel config-
ured for capture mode.
The configuration bits for each channel are stored in the CCCx registers accessible through
T2CCC. See Table 13-5 on page 74 for a description of the CCCx regi
ster.
OSC
(P1.0) T2
TR2
TL2
Timer 2 Interrupt
C/T2 = 0
C/T2 =1
TH2
TF2
RCAP2L RCAP2H
÷TPS
CCAL CCAHCCCA
CCBL CCBHCCCB
CCCL CCCHCCCC
CCDL CCDHCCCD
T2CCF
CCA Interrupt
CCA (P2.0)
CCB (P2.1)
CCC (P2.2)
CCD (P2.3)
T2CCC T2CCL T2CCH
T2CCA