Specifications

73
3706C–MICRO–2/11
AT89LP3240/6440
to occur at a negative edge, positive edge, or both (toggle). Capture inputs are sampled every
clock cycle and a new value must be held for at least 2 clock cycles to b e correctly sampled by
the device. The maximu m achievable capture rate will be determined by how fast the software
can retrieve the captured da ta. There is no protection against capture events overru
nning the
data register.
Capture events may also be triggered internally by the overflows of Timer 0 or Timer 1, or by an
event from the dual analog comparators. Any comparator event which can generate a compara-
tor interrupt may also be used as a capture event. However, Timer 2 should not be selected as
the comparator clock source when using the comp
arator as the capture trigger.
When the DAC output is enabled on P2.2 and P2.3, channels C and D cannot use their external
pin capture modes. However, those channels may still us e the timer or comparator triggers to
capture data. The same a pplies for all four channels when Port 2 is used for the external mem-
ory interface.
13.2.1 Timer 2 Operation for Capture Mode
Capture channels a
re intended to work with Timer 2 in capture mode CP/RL2 =1. Captures can
still occur when Timer 2 operates in other modes; however, the full 16-bit count range may not
be available. The TF2 flag can be used to determine if the timer overflowed before the capture
occurred. If the timer is operating in dual-slope mode (CP/RL2
=0, T2CM
1-0
=1xB), the count
direction (Up = 0 and Down = 1) at the time of the event will be captured into the channel’s
CDIRx bit in CCCx. CTCx must be cleared to 0 for all channels if Timer 2 is opera ting in Baud
Rate mode or errors may occur in the serial communication.