Specifications
75
3706C–MICRO–2/11
AT89LP3240/6440
13.3 Output Compare Mode
The Compare/Capture Array provides a variety of compare modes suitable for event timing or
waveform generation. CCA channels are configured for compare mode by setting the CCMx bit
in the associated CCCx register to 1. A compare event occurs when the 16-bit contents of a
channel’s data register match the contents of Timer 2 (TH2 and TL2). The compare event also
sets the channel’s interrupt flag CCF
x in T2CCF and may optionally clear Timer 2 to 0000H if the
CTCx bit in CCCx is set. A diagram of a CCA channel in compare mode is shown in Figure 13-3.
Figure 13-3. CCA Compare Mode Diagram
13.3.1 Waveform Generation
Each CCA channel has an associated external compare output pin: CCA (P2.0), CCB (P2.1),
CCC (P2.2) and CCD (P2.3). The CxM
2-0
bits in CCCx determine what action is taken when a
compare event occurs. The output pin may be set to 1, cleared to 0 or toggled. Output actions
take place even if the interrupt is disabled; however, the associated I/O pin must be set to the
desired output mode before the compare event occurs. The state of the compare outputs are ini-
tialized to 1 by reset. Channel
s C and D cannot use their output pin when the DAC is enabled.
These channels may still be used to generate interrupts or to clear the timebase. The same
applies to all fou r channels when Port 2 is used for the external memory interface.
Multiple compare events per channel ca n occur within a single time period, provided that the
software has time to update the compare value before the timer rea
ches the next compare point.
In this case other interrupts should be disabled or the CCA interrupt given a higher priority in
order to ensure that the interrupt is serviced in time.
A wide range of wa veform generation configurations are possib le us ing the various operating
modes of Timer 2 and the CCA. Some example configurations are detailed below. Pulse width
modulation is a specia
l case of output compare. See Section 13.4 on page 77 for more details of
PWM operation.
TL2 TH2
CCxL CCxH CCCx
Interrupt
CCx (P2.x)
T2CCCT2CCL shadow
00H 00H
CTCx
CCFx
CIENx
CxM
2-0
=
T2CCH