Specifications

78
3706C–MICRO–2/11
AT89LP3240/6440
13.4.1 Asymmetrical PWM
For Asymmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 1
(CP/RL2
=0, DCEN=0, T2CM1-0= 01B). Asymmetrical PWM uses single slope operation as
shown in Figure 13-8. The timer counts up from BOTTOM to TOP and then restarts from BOT-
TOM. In non-inverting mode, the output CCx is set on the compare match between Timer 2
(TL2, TH2) and the channel data regis ter (CCxL, CCxH), and cleared at BOTTOM. In inverting
mode, the output CCx is cleared on the compare match between Timer 2 and the data register,
a
nd set at BOTTOM. The resulting asymmetrical output waveform is left-edge aligned.
The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is
only updated at the TOP to BOTTOM overflow. The channel data register (CCxL, CCxH) is also
double-buffered such that the duty cycle is only updated at the TOP to BOTTOM overflow to pre-
vent glitches. The output frequency a nd du
ty cycle for asymmetrical PWM are given by the
following equations:
The extreme compare values represent special cases when generating a PWM waveform. If the
compare value is set equal to (or greater than) TOP, the output will remain low or high for non-
inverting and inverting modes, respectively. If the compare value is set to BOTTOM (0000H), the
output will remain high or low for non-inverting and inverting modes, respectively.
Figure 13-8. Asymmetrical (Edge-Aligned) PWM
13.4.2 Symmetrical PWM
For S
ymmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 2
or 3 (CP/RL2
= 0, DCEN = 0, T2CM1-0 =1xB). Symmetrical PWM uses dual-slope operation as
shown in Figure 13-9. The timer counts up from MIN to TOP and then counts down from TOP to
MIN. The timer is equal to TOP for exactly one clock cycle. In non-inverting mode, the output
CCx is cleared on the up-count compare match between Timer 2 (TL2, TH2) and the channel
data register (CCxL, CCxH), and set at the down-count compare match. In inverting mode, the
output CCx is set on the u
p-count compare match between Timer 2 and the data register, and
cleared at the down-count compare match. The resulting symmetrical PWM output waveform is
f
OUT
Oscillator Frequency
RCAP2H RCAP2L{,}1+
----------------------------------------------------------------
1
TPS 1+
---------------------
×=
Inverting: Duty Cycle 100%
CCxH CCxL{,}
RCAP2H RCAP2L{,}1+
----------------------------------------------------------------
×=
Non-Inverting: Duty Cycle 100%
RCAP2H RCAP2L{,}CCxH CCxL{,}– 1+
RCAP2H RCAP2L{,}1+
-------------------------------------------------------------------------------------------------------------
×=
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM
1-0
= 01B, DCEN = 0
Inverted
{CCxH,CCxL}
Non-inverted
CCx