Specifications

8
3706C–MICRO–2/11
AT89LP3240/6440
2.2 System Configuration
The AT89LP3240/6440 supports several system configuration options. Nonvolatile options are
set through user fuses that must be programmed through the flash programming interface. Vola-
tile options are controlled by software through individual bits of special function registers (SFRs).
The AT89LP3240/6440 must be properly configured before correct operation c
an occur.
2.2.1 Fuse Options
Table 2-1 lists the fusable options for the AT89LP3240/6440. These options maintain their state
even when the device is powered off, but can only be changed with an external device program-
mer. For more information, see Section 25.7 “User Configuration Fuses” on page 164.
2.2.2 Software Options
Table 2-2 lists some important software configuration bits that affect operation at the
system
level. These can be changed by the application software but are set to their default values upon
any reset. Most peripherals also have multipe configura tion bits that are not listed here.
Table 2-1. User Configuration Fuses
Fuse Name Description
Clock Source
Selects between the High Speed Crystal Oscillator, Low Speed
Crystal Oscillator, External Clock or Internal RC Oscillator for the
source of the system clock.
Start-up Time Selects time-out delay for the POR/BOD/PWD wake-up period.
Reset Pin Enable Configures the RST
pin as a reset input or general purpose I/O
Brown-Out Detector Enable Enables or disables the Brown-out Detector
On-Chip Debug Enable
Enables or disables On-Chip Debug. OCD must be enabled prior to
using an in-circuit debugger with the device.
In-System Programming Enable Enables or disables In-System Programming.
User Signature Programming Enable Enables or disab
les programming of User Signature array.
Default Port State
Configures the default port state as input-only mode (tristated) or
quasi-bidirectional mode (weakly pulled high).
In-Application Programming Enable Enables or disabled In-Application (self) Programming
Table 2-2. Important Software Configuration Bits
Bit(s) SFR Location Description
PxM0.y
PxM1.y
P0M0, P0M1, P1M0, P1M1,
P2M0, P2M1, P3M0, P3M1,
P4M0, P4M1
Configures the I/O mode of Port x Pin y to be one of input-only, quasi-
bidirectional, push-pull output or open-drain. The default state is
controlled by the Default Port State fuse above
CDV
2-0
CLKREG.3-1 Selects the division ratio between the oscillator and the system clock
TPS
3-0
CLKREG.7-4 Selects the division ratio between the system clock and the timers
ALES AUXR.0 Enables/disables toggling of ALE
EXRAM AUXR.1
Enables/disables access to on-chip memories that are mapped to the
external data memory address space
WS
1-0
AUXR.3-2
Selects the number of wait states when accessing external data
memory
XSTK AUXR.4 Congifures the hardware stack to be in RAM or extra RAM
DMEN MEMCON.3 Enables/disables access to the on-chip flash data memory
IAP MEMCON.7 Enbles/disables the self programming feature when the fuse allows