Specifications

80
3706C–MICRO–2/11
AT89LP3240/6440
Figure 13-10. Phase and Frequency Correct Symmetrical (Center-Aligned) PWM
Figure 13-11. Phase Correct Symmetrical (Center-Aligned) PWM
13.4.3 Multi-Phasic PWM
The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS
2-0
bits in T2MOD. The AT89LP3240/6440 provides 1 out of 2, 1 out of 3, 1 out of 4 and 2 out of 4
phase modes (See Table 13-6). In Multi-phasic mode the PWM outputs on CCA, CCB, CCC and
CCD are connected to a one-hot shift register that selectively enables and disables the outputs
(See Figure 13-12). Compare points on disabled channels are blocked from toggling the output
as if the compare valu
e was set equal to TOP. The PHSD bit in T2MOD controls the direction of
the shift register. Example waveforms are shown in Figure 13-14 on page 82. In order to use
multi-phasic PWM, the associated channels must be configured for PWM operation. Non-PWM
channels are not affected by multi-phasic operation. However, their locations in the shift register
are maintained such that some periods in the PWM outpu
ts may not have any pulses as shown
in Figure 13-13.
The PHS
2-0
bits may only be modified when the timer is not operational (TR2 = 0). Updates to
PHSD are allowed at any time. Note that channels C and D in 1:2 phase mode and channel D in
1:3 phase mode operate normally.
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM
1-0
= 10B, DCEN = 0
Inverted
{CCxH,CCxL}
Non-Inverted
CCx
Duty Cycle Updated
{RCAP2H,RCA2L}
CP/RL2 = 0, T2CM
1-0
= 11B, DCEN = 0
Inverted
{CCxH,CCxL}
Non-Inverted
CCx
Duty Cycle Updated