Specifications

82
3706C–MICRO–2/11
AT89LP3240/6440
Figure 13-14. Multi-Phasic PWM Modes
14. External Interrupts
The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP3240/6440 may be used as external inter-
rupt sources. The external interrupts can be programmed to be level-activated or transition-
activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is
triggered by a detected low a t the INTx
pin. If ITx = 1, external interrupt x is edge-triggered. In
this mode if successive samples of the INTx
pin show a high in one cycle and a low in the next
cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the
external interrupt pins are sampled once each clock cycle, an input high or low should hold for at
least 2 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the
external source has to hold the request pin high for at le
ast two clock cycles, and then hold it low
for at least two clock cycles to ensure that the transition is seen so that interrupt request flag IEx
will be set. IEx will be automatically cleared by the CPU when the service routine is called if gen-
erated in edge-triggered mode. If the external interrupt is level-activated, the external source has
to hold the request active until the requested interrupt is act
ually generated. Then the external
source must dea ctivate the request before the interrupt service routine is completed, or else
CCA
CCB
CCC
CCD
CCA
CCB
CCC
CCD
CCA
CCB
CCC
CCD
PHSD
CCA
CCB
CCC
CCD
PHSD
CCA
CCB
CCC
CCD
PHS = 000B
PHS = 001B
PHS = 010B
PHS = 011B
PHS = 100B