Specifications
99
3706C–MICRO–2/11
AT89LP3240/6440
Figure 17-1. SPI Block Diagram
The interconnection between master and slave CPUs with SPI is shown in Figure 17-2. The four
pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock
(SCK), and Slave Select (SS
). The SCK pin is the clock output in master mode, but is the clock
input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also
notice that MOSI connects to MOSI and MISO to MISO. By default SS
/P1.4 is an input to both
master and slave devices.
In slave mode, SS
must be driven low to select an individual device as a slave. When SS is held
low, the SPI is activated, and MISO becomes an output if configured so by the user. All other
pins are inputs. When SS
is driven high, all pins are inputs, and the SPI is passive, which means
that it will not receive incoming data. Note that the SPI logic will be reset once the SS
pin is
driven high. The SS
pin is us eful for packet/byte synchronization to keep the slave bit cou nter
synchronous with the master clock generator. When the SS
pin is driven high, the SPI slave will
immediately reset the send and receive logic, and drop any partially received data in the Shift
Register.The slave may ignore SS
by setting its SSIG bit in SPSR. When SSIG = 1, the slave is
always enabled and operates in 3-wire mode. However, the slave output on MISO may still be
disabled by setting DISSO=1.
The In-System Programming (ISP) interface also uses the SPI pins. Although the ISP protocol is
SPI-based, the SS
pin has special meaning and must be driven by the master as a frame delim-
iter. SS
cannot be tied to ground for ISP to function correctly.
Oscillator
8-bit Shift Register
Read Data Buffer
Pin Control Logic
SPI Control
SPI Status Register
SPI Interrupt
Request
Internal
Data Bus
Select
SPI Clock (Master)
Divider
÷4/÷8/÷32/÷64
SPI Control Register
8
8
8
SPIF
WCOL
SPR1
MSTR
TSCK
Clock
Logic
MSB
S
M
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
MSTR
SPE
DORD
LSB
S
M
M
S
MISO
P1.6
MOSI
P1.5
SCK
1.7
SS
P1.4
SPR0
SPE
Write Data Buffer
MODF
TXE
ENH
TSCK
01
T1 OVF
DISSO
SSIG