Specifications

Cinterion
®
ALAS5V Hardware Interface Description
2.1 Application Interface
67
 ALAS5V_HID_v00.030a 2019-03-20
Confidential / Preliminary
Page 27 of 124
PCIe PCIE_RX_N I According to PCI Express Specifica-
tion, Revision 2.0/2.1 (one lane, 5
GBit/s)
PCIE_RX_P
PCIE_TX_N O
PCIE_TX_P
PCIE_CLK_N I/O
PCIE_CLK_P
PCIE_-
CLK_REQ
IO V
OL
max = 0.45V at I = 2mA
V
OL
nom = 0.1V at I = 100µA
V
OH
min = 1.30V at I = -2mA
V
OH
nom = 1.65V at I = -100µA
V
OH
max = 1.84V
V
IL
max = 0.50V
V
IH
min = 1.30V
V
IH
max = 2.0V
I
IHPD
= 27.5µA…97.5µA
I
ILPU
= -27.5µA…-97.5µA
I
High-Z max
= ±1µA
Additional PCIe control sig-
nals
PCIE_HOST_
RST
O
PCIE_HOST_
WAKE
I
I
2
C inter-
face
I2CDAT1 I/O V
IL
max = 1.30V
V
IH
min = 0.50V
V
IH
max = 2.0V
V
OL
max = 0.3V at I = 3mA
V
OH
max = 1.84V
I
ILPU
= -27.5µA…-97.5µA
Open Drain Output (internal
pull up)
External pull up resistors
required.
Maximum load 510 Ohm.
I2CCLK1 O
JTAG inter-
face
JTAG_SRST I V
OL
max = 0.45V at I = 2mA
V
OL
nom = 0.1V at I = 100µA
V
OH
min = 1.30V at I = -2mA
V
OH
nom = 1.65V at I = -100µA
V
OH
max = 1.84V
V
IL
max = 0.50V
V
IH
min = 1.30V
V
IH
max = 2.0V
I
IHPD
= 27.5µA…97.5µA
I
ILPU
= -27.5µA…-97.5µA
I
High-Z max
= ±1µA
Debug interface.
Test point recommended for
all JTAG lines.
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TRST
JTAG_TDO O
JTAG_WD_-
DISABLE
IV
IL
max = 0.3V at -100µA
V
IH
min = 1.50V at 100µA
V
IH
max = 2.0V
High during reset and start-
up does disable the watch-
dog timer (jumper to VEXT).
There is a 2k2Ohm decou-
pling resistor between
JTAG_WD_DISABLE and
GPIO17.
JTAG_
PS_HOLD
IV
IH
min = 1.65V at 680µA
V
IL
max = 0.20V at 680µA
V
OH
max = 1.84V
V
OH
min = 1.30V at 150µA
V
OL
max = 0.5V at -200µA
High holds the power supply
during debugging (jumper to
VEXT).
Table 4: Signal description
Function Signal name IO Signal form and level Comment