Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.1.1 Pad Assignment
- 2.1.2 Signal Properties
- 2.1.3 USB Interface
- 2.1.4 Serial Interface ASC0
- 2.1.5 Serial Interface ASC1
- 2.1.6 Inter-Integrated Circuit Interface
- 2.1.7 UICC/SIM/USIM Interface
- 2.1.8 Enhanced ESD Protection for SIM Interfaces
- 2.1.9 Digital Audio Interface
- 2.1.10 Analog-to-Digital Converter (ADC)
- 2.1.11 RTC Backup
- 2.1.12 GPIO Interface
- 2.1.13 Control Signals
- 2.1.14 JTAG Interface
- 2.1.15 eMMC Interface
- 2.2 GSM/UMTS/LTE Antenna Interface
- 2.3 GNSS Antenna Interface
- 2.4 Sample Application
- 2.1 Application Interface
- 3 GNSS Interface
- 4 Operating Characteristics
- 5 Mechanical Dimensions and Mounting
- 6 Regulatory and Type Approval Information
- 7 Document Information
- 8 Appendix
Cinterion
®
ALAS5V Hardware Interface Description
2.1 Application Interface
67
ALAS5V_HID_v00.030a 2019-03-20
Confidential / Preliminary
Page 33 of 124
2.1.6 Inter-Integrated Circuit Interface
ALAS5V provides an Inter-Integrated Circuit (I
2
C) interface. I
2
C is a serial, 8-bit oriented data
transfer bus for bit rates up to 400kbps in Fast mode. It consists of two lines, the serial data line
I2CDAT and the serial clock line I2CCLK. The module acts as a single master device, e.g. the
clock I2CCLK is driven by the module. I2CDAT is a bi-directional line. Each device connected
to the bus is software addressable by a unique 7-bit address, and simple master/slave relation-
ships exist at all times. The module operates as master-transmitter or as master-receiver. The
customer application transmits or receives data only on request of the module.
The applications’ I
2
C interface can be powered via the VEXT line of ALAS5V. If connected to
the VEXT line, the I
2
C interface will properly shut down when the module enters the Power
Down mode.
In the application I2CDAT and I2CCLK lines need to be connected to a positive supply voltage
(e.g., VEXT) via a pull-up resistor. For electrical characteristics please refer to Table 4.
Figure 8: I
2
C interface connected to VEXT
Note: Good care should be taken when creating the PCB layout of the host application: The
traces of I2CCLK and I2CDAT should be equal in length and as short as possible.
I2CCLK
I2CDAT
GND
I2CCLK
I2CDAT
GND
Module Application
VEXT
R pull up
R pull up