Specifications

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Cinterion

ALAS5V Hardware Interface Description

4.2 Power Up/Power Down Scenarios



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Page 71 of 124

PCIE_CLK_M P17 Tri/PCIe Tri/PCIe 2 packets activity

(11s and 13s)

Tri/PCIe

PCIE_RX_P T12 Tri/PCIe Tri/PCIe 2 packets activity

(11s and 13s)

Tri/PCIe

PCIE_RX_M T13 Tri/PCIe Tri/PCIe 2 packets activity

(11s and 13s)

Tri/PCIe

PCIE_TX_P T15 Tri/PCIe Tri/PCIe 2 packets activity

(11s and 13s)

Tri/PCIe

PCIE_TX_M T16 Tri/PCIe Tri/PCIe 2 packets activity

(11s and 13s)

Tri/PCIe

GPIO12 E12 Tri PD PD PD

GPIO13 E11 Tri PD PD PD

GPIO14 E10 Tri PD PD PD

ANT_GNSS_ DC A17 L L L L

GNSS_EN D13 PD PD PD PD

ADC1_IN D10 Tri Tri Tri Tri

ADC2_IN D11 Tri Tri Tri Tri

ADC4_IN D8 Tri Tri Tri Tri

ADC5_IN D9 Tri Tri Tri Tri

JTAG_WD_

DISABLE

M8 Tri PD PD --> H H

JTAG_TCK C18 L H H H

JTAG_TMS D14 L H H H

JTAG_TRST D15 Tri PD PD PD

JTAG_TDI D16 L H H H

JTAG_SRST D17 L H H H

JTAG_TDO D18 L H H H

JTAG_PS_

HOLD

E13 Tri PD --> H H H

EMMC_D0 N15 Tri PD 50ms PU and 950ms

50ms PU and

950ms PD

EMMC_D1 M14 Tri PD 50ms PU and 950ms

50ms PU and

950ms PD

EMMC_D2 N14 Tri PD 50ms PU and 950ms

50ms PU and

950ms PD

EMMC_D3 P14 Tri PD 50ms PU and 950ms

50ms PU and

950ms PD

EMMC_D4 N12 Tri L L L

EMMC_D5 N13 Tri L L L

EMMC_D6 M13 Tri L L L

EMMC_D7 P12 Tri L L L

EMMC_CLK P15 Tri PD --> L 50ms CLK and

950ms PD

50ms CLK and

950ms PD

EMMC_CMD P13 Tri PD 50ms PU and 950ms

50ms PU and

950ms PD

EMMC_DETECT L7 Tri PD PD PD

EMMC_PWR L15 L L 50ms 2.9V and

950ms L

50ms 2.9V and

950ms L

Table 22: Signal states

Signal name Pad no. Reset phase

(ignition)

0 - 100ms

Hardware init

100ms - 5s

Firmware init

5s - 32s

System active

>32s