Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.2 RF Antenna Interface
- 3 Operating Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
- 7 Appendix
Cinterion
®
PDS5-E/PDS5-US Hardware Interface Overview
2.1 Application Interface
17
PDS5_HIO_v04.000 2018-09-17
Confidential / Preliminary
Page 15 of 35
2.1.6 I
2
C Interface
I
2
C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It con-
sists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module acts
as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-direc-
tional line. Each device connected to the bus is software addressable by a unique 7-bit ad-
dress, and simple master/slave relationships exist at all times. The module operates as master-
transmitter or as master-receiver. The customer application transmits or receives data only on
request of the module.
The I
2
C interface can be powered via the V180 line of PDS5-E/PDS5-US. If connected to the
V180 line, the I
2
C interface will properly shut down when the module enters the Power Down
mode.
Note: Good care should be taken when creating the PCB layout of the host application: The
traces of I2CCLK and I2CDAT should be equal in length and as short as possible.
2.1.7 SPI Interface
The Serial Peripheral Interface (SPI) is a synchronous serial interface for control and data
transfer between PDS5-E/PDS5-US and the external application. Only one application can be
connected to the SPI and the interface supports only master mode. The transmission rates are
up to 6.5Mbit/s. The SPI interface comprises the two data lines MOSI and MISO, the clock line
SPI_CLK a well as the chip select line SPI_CS.