Specifications

Cinterion
®
PLS62-W Hardware Interface Overview
2.1 Application Interface
29
t PLS62-W_hio_v02.010a 2020-08-18
Public / Released
Page 13 of 50
2.1.2 Serial Interface ASC0
PLS62-W offers an 8-wire unbalanced, asynchronous modem interface ASC0 conforming to
ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITU-T
V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit
or inactive state).
PLS62-W is designed for use as a DCE. Based on the conventions for DCE-DTE connections
it communicates with the customer application (DTE) using the following signals:
• Port TXD @ application sends data to the module’s TXD0 signal line
• Port RXD @ application receives data from the module’s RXD0 signal line
Figure 3: Serial interface ASC0
Features:
• Includes the data lines TXD0 and RXD0, the status lines RTS0 and CTS0 and, in addition,
the modem control lines DTR0, DSR0, DCD0 and RING0.
• The RING0 signal serves to indicate incoming calls and other types of URCs (Unsolicited
Result Code). It can also be used to send pulses to the host application, for example to
wake up the application from power saving state.
• Configured for 8 data bits, no parity and 1 stop bit.
• ASC0 can be operated at fixed bit rates from 1,200bps up to 3Mbps.
• Autobauding supports bit rates from 1,200bps up to 230,400bps.
• Supports RTS0/CTS0 hardware flow control. The hardware hand shake line RTS0 has an
internal pull down resistor causing a low level signal, if the line is not used and open.
Although hardware flow control is recommended, this allows communication by using only
RXD and TXD lines.
• Wake up from SLEEP mode by RTS0 activation.