Specifications

Cinterion
®
PLS62-W Hardware Interface Overview
2.1 Application Interface
29
t PLS62-W_hio_v02.010a 2020-08-18
Public / Released
Page 14 of 50
2.1.3 Serial Interface ASC1
Four PLS62-W GPIO lines can be configured as ASC1 interface signals to provide a 4-wire un-
balanced, asynchronous modem interface ASC1 conforming to ITU-T V.24 protocol DCE sig-
nalling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are
0V (for low data bit or active state) and 1.8V (for high data bit or inactive state).
PLS62-W is designed for use as a DCE. Based on the conventions for DCE-DTE connections
it communicates with the customer application (DTE) using the following signals:
• Port TXD @ application sends data to module’s TXD1 signal line
• Port RXD @ application receives data from the module’s RXD1 signal line
Figure 4: Serial interface ASC1
Features
• Includes only the data lines TXD1 and RXD1 plus RTS1 and CTS1 for hardware hand-
shake.
• On ASC1 no RING line is available.
• Configured for 8 data bits, no parity and 1 or 2 stop bits.
• ASC1 can be operated at fixed bit rates from 1,200 bps to 921,600 bps.
• Autobauding supports bit rates from 1,200bps up to 230,400bps.
• Supports RTS1/CTS1 hardware flow. The hardware hand shake line RTS0 has an internal
pull down resistor causing a low level signal, if the line is not used and open. Although hard-
ware flow control is recommended, this allows communication by using only RXD and TXD
lines.