Specifications

Cinterion
®
PLS62-W Hardware Interface Overview
2.3 Sample Application
29
t PLS62-W_hio_v02.010a 2020-08-18
Public / Released
Page 29 of 50
Figure 15: Schematic diagram of PLS62-W sample application
PWR_IND
V180
ASC0 (including GPIO1...GPIO3 for
DSR0, DTR0, DCD0 and GPIO24 for
RING0)/ SPI_CLK (for DSR0)
GPIO16...GPIO19/
ASC1/
SPI
8
4
CCVCCx
CCRSTx
CCCLKx
CCINx
CCIOx
SIM
220nF
1nF
I2CCLK
I2CDAT
2.2k***
V180
GPIO4 (FST_SHDN)
GPIO5 (STATUS)
GPIO6 (PWM2)
GPIO7 (PWM1)
GPIO8 (COUNTER)
GPIO11...GPIO15
GPIO25
GPIO26
(SIM_SWITCH)
LED
GND
GND
GND
ANT_MAIN
BATT+
RF
Power suppl
y
Main antenna
PLS62
All SIM components should be
close to card holder. Keep SIM
wires low capacitive.
*10pF
*10pF
* Add optional 10pF for SIM protection
against RF (internal Antenna)
150µF,
Low ESR!
33pF
Bl ocki ng **
Blocking**
Blocking**
PWR_IND
BATT+
BB
53
204
GPIO20...GPIO23
4
Blocking**
2.2k***
3
USB
150µF,
Low ESR!
33pF
GND
GND
ANT_DRX
Diversity antenna
EMERG_OFF
IGT
BEAD*
BEAD*: It is recommended to add the
BEAD as shown to the BATT+
BB
line. The
purpose of this is to mitigate noise from
baseband power supply.
Note 1: BLM15PD121SN1D MURATA Ind
Chip Bead (120Ohm 25% 100MHz Ferrite
1.3A) is recommended in this case. For
details please visit www.murata.com.
Note 2: The Bead should be placed as
close as possible to the module.
*** I
2
C interface of the module already
has internal 1KOhm pull up resistor to
V180 inside the module. Please take
this into consideration during
application design.
EMERG_OFF
IGT
V180
VDDLP
VDDLP
E.g., 100k
E.g., VBATT
0R
(not mounted )
100k
10k
1nF
100k
1nF
47k
VDDLP
VDDLP
1k