Specifications

Cinterion
®
PLSx3 Hardware Interface Description
2.1 Application Interface
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t PLSx3_HID_v01.003 2021-03-12
Public / Released
Page 30 of 121
Notes: No data must be sent over the ASC0 interface before the interface is active and ready
to receive data (see Section 3.2.1).
2.1.5 Serial Interface ASC1
Four PLSx3 GPIO lines can be configured as ASC1 interface signals to provide a 4-wire unbal-
anced, asynchronous modem interface ASC1 conforming to ITU-T V.24 protocol DCE signal-
ling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V
(for low data bit or active state) and 1.8V (for high data bit or inactive state). For electrical char-
acteristics please refer to Table 3.
PLSx3 is designed for use as a DCE. Based on the conventions for DCE-DTE connections it
communicates with the customer application (DTE) using the following signals:
• Port TXD @ application sends data to module’s TXD1 signal line
• Port RXD @ application receives data from the module’s RXD1 signal line
Figure 6: Serial interface ASC1
Features
• Includes only the data lines TXD1 and RXD1 plus RTS1 and CTS1 for hardware hand-
shake.
• On ASC1 no RING line is available.
• Configured for 8 data bits, no parity and 1 or 2 stop bits.
• ASC1 can be operated at fixed bit rates from 300 bps to 921,600bps.
• Supports RTS1/CTS1 hardware flow. The hardware hand shake line RTS1 has an internal
pull down resistor causing a low level signal, if the line is not used and open. Although hard-
ware flow control is recommended, this allows communication by using only RXD and TXD
lines.
Notes: The ASC1 interface lines are originally available as GPIO lines. If configured as ASC1
lines, the GPIO lines are assigned as follows:
GPIO16-->RXD1
GPIO17-->TXD1
GPIO18-->RTS1
GPIO19-->CTS1
Configuration is done by AT command (see [1]). The configuration is non-volatile and becomes
active after a module restart.