Specifications

Cinterion
®
PLSx3 Hardware Interface Description
2.1 Application Interface
60
t PLSx3_HID_v01.003 2021-03-12
Public / Released
Page 27 of 121
2.1.3 USB Interface
PLSx3 supports a USB 2.0 High Speed (480Mbit/s) device interface that is Full Speed (12Mbit/
s) compliant. The impedances, serial and pull up resistors are implemented according to “Uni-
versal Serial Bus Specification Revision 2.0”
1
, No further additional components are required.
The external application is responsible for supplying the VUSB_IN line. This line is used for ca-
ble detection only. The USB part (driver and transceiver) is supplied by means of BATT+. This
is because PLSx3 is designed as a self-powered device compliant with the “Universal Serial
Bus Specification Revision 2.0”.
Figure 4: USB circuit
To properly connect the module's USB interface to the external application, a USB 2.0 compat-
ible connector and cable or hardware design is required. For more information on the USB re-
lated signals see Table 3. Furthermore, the USB modem driver distributed with PLSx3 needs
to be installed.
While a USB connection is active, the module will never switch to SLEEP mode. Only if the USB
interface is in Suspend mode, the module is able to switch to SLEEP mode.
1. The specification is ready for download on http://www.usb.org/developers/docs/
VBUS
DP
DN
VREG (3V075)
BATT+
USB_DP
2)
lin. reg.
GND
Module
Detection only
VUSB_IN
USB part
1)
1)
All serial (including R
S
) and pull-up resistors for data lines are implemented.
USB_DN
2)
2)
If the USB interface is operated in High Speed mode (480MHz), it is recommended to take
special care routing the data lines USB_DP and USB_DN. Application layout should in this
case implement a differential impedance of 90 ohms for proper signal integrity.
R
S
R
S
SMT