Product Info

Cinterion
®
TX62-W(-B/-C)/TX82-W Hardware Interface Description
1.4 Circuit Concept
19
t TX62-W_TX62-W-x_TX82-W_HID_v01.000 2021-05-19
Confidential / Preliminary
Page 18 of 154
Figure 4: TX62-W-B block diagram
19.2MHz
32.768 kHz
19.2MHz
with
Temp.Sensor
X-tal:
Control interface
Reset
HWID’s
GPIO’s
GNSS
LTE
Antenna LGA Pads
LGA Pads
GSM/CatM1/CatNB
Baseband controller
with integrated memory
ADC
RF
Interru pt
BATT+_RF
RF Transceiver
BATT+_RF
Power Management
IC
Power Supply
Power Supply
Serial (ASC0)
Serial (ASC1/GPIO)
USB 2.0
USIM
CCIN
FST_SHDN
STATUS (GPIO)
SUSPEND_MON
SIM_SWITCH (GPIO)
GPIO (not shared)
I
2
C
SPI (GPIO)
VUSIM
ADC1
EMERG_RST
ON
V180
VCORE
BATT+
RF
BATT+
BB
eUICC (optional)
I/Q-signals
(2x2)
SDR _RX_ L T E
RF_CLK1
SDR_GNSS
LTE PA + PAM
BATT+
PS_HOL D
REFE 1...2 _
CLK_DATA
4
GPDATA
STMR_SYNC
BATT+
IN
EN
OUT
LDO
USB_VDDA
_3P3
GPIO
REFE 2_CLK_DATA
2
RF Part
eUICC
(MFF-XS eUICC)
5
SDR_TX_L B_ L TE
SDR_TX_MB_LTE
GN SS
SAW f ilter
Matching
B71_ RX
3
4
8
3
7
2
4