Product Info
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.2 RF Antenna Interface
- 2.3 GNSS Interface
- 2.4 Sample Application
- 3 Operating Characteristics
- 3.1 Operating Modes
- 3.2 Power Up/Power Down Scenarios
- 3.3 Power Saving
- 3.4 Power Supply
- 3.5 Operating Temperatures
- 3.6 Electrostatic Discharge
- 3.7 Blocking against RF on Interface Lines
- 3.8 Reliability Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
- 7 Appendix
Cinterion
®
TX62-W(-B/-C)/TX82-W Hardware Interface Description
1.4 Circuit Concept
19
t TX62-W_TX62-W-x_TX82-W_HID_v01.000 2021-05-19
Confidential / Preliminary
Page 19 of 154
Figure 5: TX62-W-C block diagram
Please note that the I
2
C function and some GPIO lines are available with the embedded pro-
cessing option only. Also, some GPIO lines may be shared with further functions that are also
only available with the embedded processing option. For details see Section 2.1, and Section
2.1.8.1.
19.2MHz
32.768kHz
19.2MHz
with
Temp.Sensor
X-tal:
Control interface
Reset
HWID’s
GPIO’s
GNSS
LTE
Antenna LGA Pads
LGA Pads
GSM/CatM1/CatNB
Baseband Controller
With Integrated Memory
ADC
RF
Interrupt
BATT+_RF
RF
Transceiver
BATT_RF
3
4
Power
Management
IC
Power Supply
Power Supply
ASC0
ASC1
USB 2.0
USIM
CCIN
FAST_SHDN
STATUS (GPIO)
SUSPEND_MON
SIM_SWITCH (GPIO)
GPIO (not shared)
I
2
C
SPI (GPIO)
VUSIM
ADC1
EMERG_RST
ON
V180
VCORE
BATT+RF
BATT+BB
eUICC (optional)
8
I/Q-signals
(2x2)
RX_LTE
RF_CLK1
GNSS
2
LTE PC3 PA
+ASM
BATT+
PS_HO LD
2
REFE 1...2_
CLK_DATA
4
GPDATA
STM R_SYNC
BATT+
IN
EN
OUT
LDO
USB_VDDA
_3P3
GPIO
REFE 2_CLK _ D ATA
2
RF Part
5
TX_LB_LTE
TX_MB_LTE
GN SS
SAW f ilter
B31/72_RX
B 3 1/7 2_D A_ OU T
LB LPF
B31/72 PA
B31/72 filter
HDET
2
PA _C TRL
7
4
eUI CC
(MFF-XS eUICC)