Product Info
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.2 RF Antenna Interface
- 2.3 GNSS Interface
- 2.4 Sample Application
- 3 Operating Characteristics
- 3.1 Operating Modes
- 3.2 Power Up/Power Down Scenarios
- 3.3 Power Saving
- 3.4 Power Supply
- 3.5 Operating Temperatures
- 3.6 Electrostatic Discharge
- 3.7 Blocking against RF on Interface Lines
- 3.8 Reliability Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
- 7 Appendix
Cinterion
®
TX62-W(-B/-C)/TX82-W Hardware Interface Description
2.1 Application Interface
69
t TX62-W_TX62-W-x_TX82-W_HID_v01.000 2021-05-19
Confidential / Preliminary
Page 41 of 154
2.1.8 GPIO
TX82-W, TX62-W-B and TX62-W-C have 7 GPIOs (GPIO6-7,20-23,25) and TX62-W has 6
GPIOs (GPIO7,20-23,25) for external hardware devices. Each GPIO can be configured for use
as input or output. All settings are AT command controlled. The configuration is non-volatile
and available after module restart.
The IO port driver has to be opened before using and configuring GPIOs. Before changing the
configuration of a GPIO pin (e.g. input to output) the pin has to be closed. If the GPIO pins are
not configured or the pins/driver were closed, the GPIO pins are high-Z with pull down resistor.
If a GPIO is configured to input, the pin has high-Z without pull resistor.
The following figure shows the start up behavior of the GPIOs interface.
Figure 17: GPIO start up behavior
With the embedded processing option of TX62/TX82 additional GPIOs are provided and can
be used - see below Section 2.1.8.1.
EMERG_RST
V180
GPIO6,7,20-23,25
Reset State
PD
Start up
Power supply active
Firmware
Initialization
Command Interface
Initialization
CTS0
ON
VCORE
High-Z/PD