Product Info

Cinterion
®
TX62-W(-B/-C)/TX82-W Hardware Interface Description
Figures
154
t TX62-W_TX62-W-x_TX82-W_HID_v01.000 2021-05-19
Confidential / Preliminary
Page 7 of 154
Figures
Figure 1: TX62/TX82 system overview ......................................................................... 15
Figure 2: TX82-W block diagram................................................................................... 16
Figure 3: TX62-W block diagram................................................................................... 17
Figure 4: TX62-W-B block diagram............................................................................... 18
Figure 5: TX62-W-C block diagram............................................................................... 19
Figure 6: TX62/TX82 top view: Pad assignments ......................................................... 22
Figure 7: TX62/TX82 bottom view: Pad assignments ................................................... 23
Figure 8: USB circuit ..................................................................................................... 31
Figure 9: Serial interface ASC0..................................................................................... 32
Figure 10: ASC0 startup behavior................................................................................... 33
Figure 11: Serial interface ASC1..................................................................................... 34
Figure 12: ASC1 startup behavior................................................................................... 35
Figure 13: External UICC/SIM/USIM card holder circuit ................................................. 37
Figure 14: SIM interface - enhanced ESD protection...................................................... 38
Figure 15: eUICC interface with switch for external SIM................................................. 39
Figure 16: eUICC interface without SIM switch............................................................... 40
Figure 17: GPIO start up behavior .................................................................................. 41
Figure 18: I
2
C interface connected to V180 .................................................................... 43
Figure 19: Characteristics of SPI modes......................................................................... 44
Figure 20: Status signaling with LED driver .................................................................... 45
Figure 21: Power indication circuit .................................................................................. 46
Figure 22: Fast shutdown timing ..................................................................................... 47
Figure 23: SIM switch circuit ........................................................................................... 47
Figure 24: Antenna pads (top view) ................................................................................ 58
Figure 25: Embedded Stripline with 65µm prepreg (1080) and 710µm core .................. 59
Figure 26: Micro-Stripline on 1.0mm Standard FR4 2-layer PCB - example 1................ 60
Figure 27: Micro-Stripline on 1.0mm Standard FR4 2-layer PCB - example 2................ 61
Figure 28: Micro-Stripline on 1.5mm Standard FR4 2-layer PCB - example 1................ 62
Figure 29: Micro-Stripline on 1.5mm Standard FR4 2-layer PCB - example 2................ 63
Figure 30: Routing to application‘s RF connector - top view........................................... 64
Figure 31: Sample supply voltage circuit for active GNSS antenna................................ 65
Figure 32: Schematic diagram of TX62/TX82 sample application .................................. 68
Figure 33: Sample level conversion circuit...................................................................... 69
Figure 34: Sample ON circuit .......................................................................................... 71
Figure 35: ON startup timing ........................................................................................... 72
Figure 36: Emergency restart timing ............................................................................... 73
Figure 37: Switch off behavior......................................................................................... 75
Figure 38: Low power modes with state transitions ........................................................ 79
Figure 39: Wake-up via RTS0......................................................................................... 80
Figure 40: Handshake for entering the module’s SUSPEND mode................................ 81
Figure 41: Handshake for module wake up via ON signal .............................................. 82
Figure 42: Handshake for module wake up after eDRX/PSM timer expiry ..................... 82
Figure 43: DRX based paging and power saving (SLEEP) in GSM networks ................ 83
Figure 44: DRX based paging and power saving (SLEEP) in LTE Cat M1 and
Cat NB1/2 networks ....................................................................................... 84
Figure 45: eDRX based paging and power saving in LTE Cat M1 and
Cat NB1/2 networks ....................................................................................... 85
Figure 46: eDRX/PSM based paging and power saving in LTE Cat M1 or
Cat NB1/2 networks ....................................................................................... 86
Figure 47: Power supply limits during transmit burst..................................................... 104